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[60.241.117.97]) by smtp.gmail.com with ESMTPSA id 8sm1762515pfz.12.2020.04.06.17.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Apr 2020 17:28:21 -0700 (PDT) Date: Tue, 07 Apr 2020 10:26:58 +1000 From: Nicholas Piggin Subject: Re: [RFC PATCH v2 12/13] powerpc/kernel: Do not inconditionally save non volatile registers on system call To: Benjamin Herrenschmidt , Christophe Leroy , Michael Ellerman , msuchanek@suse.de, Paul Mackerras References: <029e1064b1ad738785718221ea468c9cfc282457.1586108649.git.christophe.leroy@c-s.fr> <4ef6d617cfd34e09e9bf5a456b2e0b6d2a8a3c96.1586108649.git.christophe.leroy@c-s.fr> <1586135554.pnqaj0giue.astroid@bobo.none> <48d3e2e5-318f-011e-a59b-ec89bd7b76d2@c-s.fr> In-Reply-To: <48d3e2e5-318f-011e-a59b-ec89bd7b76d2@c-s.fr> MIME-Version: 1.0 User-Agent: astroid/0.15.0 (https://github.com/astroidmail/astroid) Message-Id: <1586218971.lolwg4f0lh.astroid@bobo.none> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Christophe Leroy's on April 7, 2020 4:18 am: >=20 >=20 > Le 06/04/2020 =C3=A0 03:25, Nicholas Piggin a =C3=A9crit=C2=A0: >> Christophe Leroy's on April 6, 2020 3:44 am: >>> Before : 347 cycles on null_syscall >>> After : 327 cycles on null_syscall >>=20 >> The problem I had doing this is that signal delivery wnats full regs, >> and you don't know if you have a signal pending ahead of time if you >> have interrupts enabled. >>=20 >> I began to try bailing out back to asm to save nvgprs and call again. >> I think that can be made to work, but it is more complication in asm, >> and I soon found that 64s CPUs don't care about NVGPRs too much so it's >> nice to get rid of the !fullregs state. >=20 > I tried a new way in v3, please have a look. I split=20 > syscall_exit_prepare() in 3 parts and the result is unexpected: it is=20 > better than before the series (307 cycles now versus 311 cycles with=20 > full ASM syscall entry/exit). Great! Well I don't really see a problem with how you changed the C code=20 around. I'll have to look at the assembly but I don't think it would=20 have caused a problem for 64s. Thanks, Nick =