From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=3.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CCD5C2BA1A for ; Tue, 7 Apr 2020 00:53:29 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BE08E20768 for ; Tue, 7 Apr 2020 00:53:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CqEj5G+G" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BE08E20768 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48x86F6xR8zDqss for ; Tue, 7 Apr 2020 10:53:25 +1000 (AEST) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::441; helo=mail-pf1-x441.google.com; envelope-from=npiggin@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=CqEj5G+G; dkim-atps=neutral Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 48x84P1Y8QzDqM5 for ; Tue, 7 Apr 2020 10:51:47 +1000 (AEST) Received: by mail-pf1-x441.google.com with SMTP id a24so8462843pfc.8 for ; Mon, 06 Apr 2020 17:51:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=date:from:subject:to:cc:references:in-reply-to:mime-version :user-agent:message-id:content-transfer-encoding; bh=tAw8KW0bFK0Yz8fIQWiF5l2yjocFDcbB0anIbqS6PMQ=; b=CqEj5G+G1Sj4eY6jp4z1gwYVVfP3ETQnuFn7UF14pAzWnqbjMtwoznXsx7fbhBZ3xx SfE7Wcbx04ZI0XVPq+w0HsmW6uLefMOG6+x/k1RYvEaUjUoTBZ1xMHzuJYN2VfDMo+rN xwbW3q//wywrDHb3RgR8RnRdXvYXUfHFmvXA2GjclllReOVuFY3IcPOr6lySEPouZvTI SZaWhnsVBPesQsSW59bWFclTF+EZ2amlNN+n38mbG9tssPXWypwA/q2SGOfFgqnfj9HI XIHrmdopSuoZ1bTv193cBLOYcZJqpaWksg9cLZ60IFbf5laJuNZjUXuIXybMHqhnZunN T98g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:subject:to:cc:references:in-reply-to :mime-version:user-agent:message-id:content-transfer-encoding; bh=tAw8KW0bFK0Yz8fIQWiF5l2yjocFDcbB0anIbqS6PMQ=; b=DvRpr3Cj4Qg7OZ6jIUMFRUpXgdARYt48wCtYxfQDYRV8ETceDeTzM7u12mU7QjVjrw 4iwCOM4VvKrNRYleathMWslS5KqfzUEJ/PlFoDXY5mZcJImqUv37gISk31DcGfVKZE56 TKesi4LSygjVCtvzvvKOmDFBkmfHiEiJvCneEKk26TXZFEe9MPCIay4Dn+zetbcfVslY pla3c3lL1vEahxf7BCxOpAgmQwim8+rOciMPmzlonR1Vet30/9fKiJZMts9D2awVvpGm C0yCobJsk/Y6DBM41x0f0Gr+0wy5jLkYb/cmI75MY7GUro51EgfheGCtCM/KDX3gQ1sk IppA== X-Gm-Message-State: AGi0PuYfx+1SQapW6txpuR/yLAHjyAHKPOpzqcLgFIoJ/iECVRhpokp+ xRUy08SM/XynVUZxNdwv4PA= X-Google-Smtp-Source: APiQypJiXLxaPiaqtXc+2hUQni5NRszaSjpfE6ESZh4OGo/SjydSw+b7jjk1VPM3FGSAKr2kgTwqcA== X-Received: by 2002:a65:670e:: with SMTP id u14mr1842173pgf.264.1586220705440; Mon, 06 Apr 2020 17:51:45 -0700 (PDT) Received: from localhost (60-241-117-97.tpgi.com.au. [60.241.117.97]) by smtp.gmail.com with ESMTPSA id o15sm11699220pgj.60.2020.04.06.17.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Apr 2020 17:51:44 -0700 (PDT) Date: Tue, 07 Apr 2020 10:50:20 +1000 From: Nicholas Piggin Subject: Re: [RFC PATCH v3 05/15] powerpc/irq: Add helpers to get and set regs->softe To: Benjamin Herrenschmidt , Christophe Leroy , Michael Ellerman , msuchanek@suse.de, Paul Mackerras References: <5aeaa33383e833f6eca30893fbd188b88e019eaa.1586196948.git.christophe.leroy@c-s.fr> In-Reply-To: MIME-Version: 1.0 User-Agent: astroid/0.15.0 (https://github.com/astroidmail/astroid) Message-Id: <1586219567.cl8bye6kgu.astroid@bobo.none> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Christophe Leroy's on April 7, 2020 4:16 am: > regs->softe doesn't exist on PPC32. >=20 > Add helpers to get and set regs->softe. > Those helpers will void on PPC32. >=20 > Signed-off-by: Christophe Leroy > --- > arch/powerpc/include/asm/hw_irq.h | 21 +++++++++++++++++++-- > 1 file changed, 19 insertions(+), 2 deletions(-) >=20 > diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm= /hw_irq.h > index e0e71777961f..e69466867d5f 100644 > --- a/arch/powerpc/include/asm/hw_irq.h > +++ b/arch/powerpc/include/asm/hw_irq.h > @@ -39,6 +39,8 @@ > #define PACA_IRQ_MUST_HARD_MASK (PACA_IRQ_EE) > #endif > =20 > +#endif /* CONFIG_PPC64 */ > + > /* > * flags for paca->irq_soft_mask > */ > @@ -47,8 +49,6 @@ > #define IRQS_PMI_DISABLED 2 > #define IRQS_ALL_DISABLED (IRQS_DISABLED | IRQS_PMI_DISABLED) > =20 > -#endif /* CONFIG_PPC64 */ > - > #ifndef __ASSEMBLY__ > =20 > extern void replay_system_reset(void); > @@ -282,6 +282,15 @@ extern void irq_set_pending_from_srr1(unsigned long = srr1); > =20 > extern void force_external_irq_replay(void); > =20 > +static inline unsigned long get_softe(struct pt_regs *regs) > +{ > + return regs->softe; > +} > + > +static inline void set_softe(struct pt_regs *regs, unsigned long val) > +{ > + regs->softe =3D val; > +} > #else /* CONFIG_PPC64 */ > =20 > static inline unsigned long arch_local_save_flags(void) > @@ -350,6 +359,14 @@ static inline bool arch_irq_disabled_regs(struct pt_= regs *regs) > =20 > static inline void may_hard_irq_enable(void) { } > =20 > +static inline unsigned long get_softe(struct pt_regs *regs) > +{ > + return 0; > +} > + > +static inline void set_softe(struct pt_regs *regs, unsigned long val) > +{ > +} If this goes into a general shared header, I would prefer if we could do something a bit more general (at least with the name). I think get_softe() could just be replaced with arch_irq_disabled_regs(). For set, could we call it irq_soft_mask_regs_set_state()? 32 has no soft mask state in regs, so it's more obvious that it's a no-op. Or you could make 32-bit version a BUG(), and then always guard it with IS_ENABLED(). Thanks, Nick =