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[193.116.199.65]) by smtp.gmail.com with ESMTPSA id e2sm6069266pjt.2.2020.05.04.01.19.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 May 2020 01:19:58 -0700 (PDT) Date: Mon, 04 May 2020 18:19:52 +1000 From: Nicholas Piggin Subject: Re: [PATCH 1/2] powerpc/64s/hash: add torture_slb kernel boot option to increase SLB faults To: "Aneesh Kumar K.V" , linuxppc-dev@lists.ozlabs.org References: <20200503082236.17991-1-npiggin@gmail.com> <877dxsma7p.fsf@linux.ibm.com> In-Reply-To: <877dxsma7p.fsf@linux.ibm.com> MIME-Version: 1.0 Message-Id: <1588579594.33h8ri1xco.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Aneesh Kumar K.V's message of May 4, 2020 5:27 pm: > Nicholas Piggin writes: >=20 >> This option increases the number of SLB misses by limiting the number of >> kernel SLB entries, and increased flushing of cached lookaside informati= on. >> This helps stress test difficult to hit paths in the kernel. >> >> Signed-off-by: Nicholas Piggin >=20 > .... >=20 >> +{ >> + unsigned long slbie_data =3D get_paca()->slb_cache[index]; >> + unsigned long ksp =3D get_paca()->kstack; >> + >> + slbie_data <<=3D SID_SHIFT; >> + slbie_data |=3D 0xc000000000000000ULL; >> + if ((ksp & slb_esid_mask(mmu_kernel_ssize)) =3D=3D slbie_data) >> + return; >> + slbie_data |=3D mmu_kernel_ssize << SLBIE_SSIZE_SHIFT; >> + >> + asm volatile("slbie %0" : : "r" (slbie_data)); >> +} >> + >> +static void slb_cache_slbie(unsigned int index) >=20 > May be slb_cache_slbie_user()? Similar to _kernel above? Yeah that'd help. >> +{ >> + unsigned long slbie_data =3D get_paca()->slb_cache[index]; >> + >> + slbie_data <<=3D SID_SHIFT; >> + slbie_data |=3D user_segment_size(slbie_data) << SLBIE_SSIZE_SHIFT; >> + slbie_data |=3D SLBIE_C; /* user slbs have C=3D1 */ >> + >> + asm volatile("slbie %0" : : "r" (slbie_data)); >> +} >> =20 >> /* Flush all user entries from the segment table of the current process= or. */ >> void switch_slb(struct task_struct *tsk, struct mm_struct *mm) >> @@ -414,8 +449,14 @@ void switch_slb(struct task_struct *tsk, struct mm_= struct *mm) >> * which would update the slb_cache/slb_cache_ptr fields in the PACA. >> */ >> hard_irq_disable(); >> - asm volatile("isync" : : : "memory"); >> - if (cpu_has_feature(CPU_FTR_ARCH_300)) { >> + isync(); >> + if (torture_slb()) { >> + __slb_flush_and_restore_bolted(0); >=20 > s/0/SLIBA_IH_ALL or something like that?=20 IH isn't so simple. 0 isn't all, it's clear all SLBE except index zero,=20 and flush all EA lookaside data. Maybe callers should use a bool parameter though to flush kernel=20 lookaside data. Thanks, Nick