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[110.174.173.27]) by smtp.gmail.com with ESMTPSA id 12sm29174670wmg.6.2020.07.19.22.38.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jul 2020 22:38:36 -0700 (PDT) Date: Mon, 20 Jul 2020 15:38:29 +1000 From: Nicholas Piggin Subject: Re: [FIX PATCH] powerpc/prom: Enable Radix GTSE in cpu pa-features To: Bharata B Rao , linuxppc-dev@lists.ozlabs.org References: <20200720044258.863574-1-bharata@linux.ibm.com> In-Reply-To: <20200720044258.863574-1-bharata@linux.ibm.com> MIME-Version: 1.0 Message-Id: <1595223290.jz1cmk38dz.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aneesh.kumar@linux.ibm.com, Qian Cai Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Bharata B Rao's message of July 20, 2020 2:42 pm: > From: Nicholas Piggin >=20 > When '029ab30b4c0a ("powerpc/mm: Enable radix GTSE only if supported.")' > made GTSE an MMU feature, it was enabled by default in > powerpc-cpu-features but was missed in pa-features. This causes > random memory corruption during boot of PowerNV kernels where > CONFIG_PPC_DT_CPU_FTRS isn't enabled. Thanks for writing this up, I got a bit bogged down with other things. > Fixes: 029ab30b4c0a ("powerpc/mm: Enable radix GTSE only if supported.") > Reported-by: Qian Cai > Signed-off-by: Nicholas Piggin > Signed-off-by: Bharata B Rao > --- > arch/powerpc/kernel/prom.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >=20 > diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c > index 9cc49f265c86..a9594bad572a 100644 > --- a/arch/powerpc/kernel/prom.c > +++ b/arch/powerpc/kernel/prom.c > @@ -163,7 +163,8 @@ static struct ibm_pa_feature { > { .pabyte =3D 0, .pabit =3D 6, .cpu_features =3D CPU_FTR_NOEXECUTE }, > { .pabyte =3D 1, .pabit =3D 2, .mmu_features =3D MMU_FTR_CI_LARGE_PAG= E }, > #ifdef CONFIG_PPC_RADIX_MMU > - { .pabyte =3D 40, .pabit =3D 0, .mmu_features =3D MMU_FTR_TYPE_RADIX }= , > + { .pabyte =3D 40, .pabit =3D 0, > + .mmu_features =3D (MMU_FTR_TYPE_RADIX | MMU_FTR_GTSE) }, It might look better like this: { .pabyte =3D 1, .pabit =3D 2, .mmu_features =3D MMU_FTR_CI_LARGE= _PAGE }, #ifdef CONFIG_PPC_RADIX_MMU { .pabyte =3D 40, .pabit =3D 0, .mmu_features =3D MMU_FTR_TYPE_RAD= IX }, { .pabyte =3D 40, .pabit =3D 0, .mmu_features =3D MMU_FTR_TYPE_RAD= IX | MMU_FTR_GTSE }, #endif { .pabyte =3D 1, .pabit =3D 1, .invert =3D 1, .cpu_features =3D CPU_FTR= _NODSISRALIGN }, But that's bikeshedding a bit and the optional bits already put it out=20 of alignment. Thanks, Nick