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Sun, 30 Aug 2020 18:25:45 -0700 (PDT) Received: from localhost ([203.185.249.227]) by smtp.gmail.com with ESMTPSA id d1sm5201193pjs.17.2020.08.30.18.25.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Aug 2020 18:25:45 -0700 (PDT) Date: Mon, 31 Aug 2020 11:25:39 +1000 From: Nicholas Piggin Subject: Re: [PATCH 1/4] mm: fix exec activate_mm vs TLB shootdown and lazy tlb switching race To: peterz@infradead.org References: <20200828100022.1099682-1-npiggin@gmail.com> <20200828100022.1099682-2-npiggin@gmail.com> <20200828111525.GX1362448@hirez.programming.kicks-ass.net> In-Reply-To: <20200828111525.GX1362448@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Message-Id: <1598836589.75k5wmftvn.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jens Axboe , linux-arch@vger.kernel.org, "Aneesh Kumar K.V" , linux-kernel@vger.kernel.org, linux-mm@kvack.org, Andrew Morton , linuxppc-dev@lists.ozlabs.org, "David S. Miller" Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from peterz@infradead.org's message of August 28, 2020 9:15 pm: > On Fri, Aug 28, 2020 at 08:00:19PM +1000, Nicholas Piggin wrote: >=20 >> Closing this race only requires interrupts to be disabled while ->mm >> and ->active_mm are being switched, but the TLB problem requires also >> holding interrupts off over activate_mm. Unfortunately not all archs >> can do that yet, e.g., arm defers the switch if irqs are disabled and >> expects finish_arch_post_lock_switch() to be called to complete the >> flush; um takes a blocking lock in activate_mm(). >=20 > ARM at least has activate_mm() :=3D switch_mm(), so it could be made to > work. > Yeah, so long as that post_lock_switch switch did the right thing with respect to its TLB flushing. It should do because arm doesn't seem to check ->mm or ->active_mm (and if it was broken, the scheduler context switch would be suspect too). I don't think the fix would be hard, just that I don't have a good way to test it and qemu isn't great for testing this kind of thing. um too I think could probably defer that lock until after interrupts are enabled again. I might throw a bunch of arch conversion patches over the wall if this gets merged and try to move things along. Thanks, Nick