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Tue, 08 Sep 2020 00:48:52 -0700 (PDT) Received: from localhost ([203.185.249.227]) by smtp.gmail.com with ESMTPSA id s67sm18580315pfs.117.2020.09.08.00.48.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 00:48:52 -0700 (PDT) Date: Tue, 08 Sep 2020 17:48:46 +1000 From: Nicholas Piggin Subject: Re: [RFC PATCH 02/12] powerpc: remove arguments from interrupt handler functions To: Christophe Leroy References: <20200905174335.3161229-1-npiggin@gmail.com> <20200905174335.3161229-3-npiggin@gmail.com> <1599478457.27656.1.camel@po17688vm.idsi0.si.c-s.fr> In-Reply-To: <1599478457.27656.1.camel@po17688vm.idsi0.si.c-s.fr> MIME-Version: 1.0 Message-Id: <1599551224.3zoap14y55.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Christophe Leroy's message of September 7, 2020 9:34 pm: > On Mon, 2020-09-07 at 11:20 +0200, Christophe Leroy wrote: >>=20 >> Le 05/09/2020 =C3=A0 19:43, Nicholas Piggin a =C3=A9crit : >> > Make interrupt handlers all just take the pt_regs * argument and load >> > DAR/DSISR etc from that. Make those that return a value return long. >>=20 >> I like this, it will likely simplify a bit the VMAP_STACK mess. >>=20 >> Not sure it is that easy. My board is stuck after the start of init. >>=20 >>=20 >> On the 8xx, on Instruction TLB Error exception, we do >>=20 >> andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */ >>=20 >> On book3s/32, on ISI exception we do: >> andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */ >>=20 >> On 40x and bookE, on ISI exception we do: >> li r5,0 /* Pass zero as arg3 */ >>=20 >>=20 >> And regs->dsisr will just contain nothing >>=20 >> So it means we should at least write back r5 into regs->dsisr from there= =20 >> ? The performance impact should be minimal as we already write _DAR so=20 >> the cache line should already be in the cache. >>=20 >> A hacky 'stw r5, _DSISR(r1)' in handle_page_fault() does the trick,=20 >> allthough we don't want to do it for both ISI and DSI at the end, so=20 >> you'll have to do it in every head_xxx.S >=20 > To get you series build and work, I did the following hacks: Great, thanks for this. > diff --git a/arch/powerpc/include/asm/interrupt.h > b/arch/powerpc/include/asm/interrupt.h > index acfcc7d5779b..c11045d3113a 100644 > --- a/arch/powerpc/include/asm/interrupt.h > +++ b/arch/powerpc/include/asm/interrupt.h > @@ -93,7 +93,9 @@ static inline void interrupt_nmi_exit_prepare(struct > pt_regs *regs, struct inter > { > nmi_exit(); > =20 > +#ifdef CONFIG_PPC64 > this_cpu_set_ftrace_enabled(state->ftrace_enabled); > +#endif This seems okay, not a hack. > #ifdef CONFIG_PPC_BOOK3S_64 > /* Check we didn't change the pending interrupt mask. */ > diff --git a/arch/powerpc/kernel/entry_32.S > b/arch/powerpc/kernel/entry_32.S > index f4d0af8e1136..66f7adbe1076 100644 > --- a/arch/powerpc/kernel/entry_32.S > +++ b/arch/powerpc/kernel/entry_32.S > @@ -663,6 +663,7 @@ ppc_swapcontext: > */ > .globl handle_page_fault > handle_page_fault: > + stw r5,_DSISR(r1) > addi r3,r1,STACK_FRAME_OVERHEAD > #ifdef CONFIG_PPC_BOOK3S_32 > andis. r0,r5,DSISR_DABRMATCH@h Is this what you want to do for 32, or do you want to seperate ISI and DSI sides? Thanks, Nick