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[27.32.36.31]) by smtp.gmail.com with ESMTPSA id a28sm13517009pfk.50.2020.11.10.00.19.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2020 00:19:05 -0800 (PST) Date: Tue, 10 Nov 2020 18:18:59 +1000 From: Nicholas Piggin Subject: Re: [PATCH] powerpc: add compile-time support for lbarx, lwarx To: Christophe Leroy , linuxppc-dev@lists.ozlabs.org References: <20201107032328.2454582-1-npiggin@gmail.com> <311a1f6d-01ca-e35f-d145-3c643fb40f74@csgroup.eu> In-Reply-To: <311a1f6d-01ca-e35f-d145-3c643fb40f74@csgroup.eu> MIME-Version: 1.0 Message-Id: <1604995561.t19n2j4wpv.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Christophe Leroy's message of November 7, 2020 6:15 pm: >=20 >=20 > Le 07/11/2020 =C3=A0 04:23, Nicholas Piggin a =C3=A9crit=C2=A0: >> ISA v2.06 (POWER7 and up) as well as e6500 support lbarx and lwarx. >> Add a compile option that allows code to use it, and add support in >> cmpxchg and xchg 8 and 16 bit values. >=20 > Do you mean lharx ? Because lwarx exists on all powerpcs I think. Thanks all who pointed out mistakes :) Yes lharx. >=20 >>=20 >> Signed-off-by: Nicholas Piggin >> --- >> arch/powerpc/Kconfig | 3 + >> arch/powerpc/include/asm/cmpxchg.h | 236 ++++++++++++++++++++++++- >> arch/powerpc/platforms/Kconfig.cputype | 5 + >> 3 files changed, 243 insertions(+), 1 deletion(-) >>=20 >> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig >> index e9f13fe08492..d231af06f75a 100644 >> --- a/arch/powerpc/Kconfig >> +++ b/arch/powerpc/Kconfig >> @@ -266,6 +266,9 @@ config PPC_BARRIER_NOSPEC >> default y >> depends on PPC_BOOK3S_64 || PPC_FSL_BOOK3E >> =20 >> +config PPC_LBARX_LWARX >> + bool >=20 > s/LWARX/LHARX/ ? >=20 > And maybe better with PPC_HAS_LBARX_LWARX ? Yes you're right, PPC_HAS_ fits better. [...] >> +#endif >=20 > That's a lot of code duplication. Could we use some macro, in the same sp= irit as what is done in=20 > arch/powerpc/include/asm/io.h for in_be16(), in_be32(), in_be64() and fri= ends ? For now I don't get too fancy. It's a bit ugly but I'm working through a=20 generic atomics conversion patch and trying to also work out a nice form for larx/stcx operation generation macros, I'll look at tidying up this some time after then. Thanks, Nick