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Thu, 03 Dec 2020 14:13:50 -0800 (PST) Received: from localhost ([2001:8004:1480:55d9:df22:9c5d:bdf7:7c2b]) by smtp.gmail.com with ESMTPSA id kb12sm318120pjb.2.2020.12.03.14.13.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Dec 2020 14:13:49 -0800 (PST) Date: Fri, 04 Dec 2020 08:13:40 +1000 From: Nicholas Piggin Subject: Re: [MOCKUP] x86/mm: Lightweight lazy mm refcounting To: Andy Lutomirski , Peter Zijlstra References: <7c4bcc0a464ca60be1e0aeba805a192be0ee81e5.1606972194.git.luto@kernel.org> <20201203084448.GF2414@hirez.programming.kicks-ass.net> In-Reply-To: <20201203084448.GF2414@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Message-Id: <1607033145.hcppy9ndl4.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch , X86 ML , Arnd Bergmann , Linux-MM , Catalin Marinas , Rik van Riel , LKML , Dave Hansen , Will Deacon , Mathieu Desnoyers , linuxppc-dev Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Peter Zijlstra's message of December 3, 2020 6:44 pm: > On Wed, Dec 02, 2020 at 09:25:51PM -0800, Andy Lutomirski wrote: >=20 >> power: same as ARM, except that the loop may be rather larger since >> the systems are bigger. But I imagine it's still faster than Nick's >> approach -- a cmpxchg to a remote cacheline should still be faster than >> an IPI shootdown.=20 >=20 > While a single atomic might be cheaper than an IPI, the comparison > doesn't work out nicely. You do the xchg() on every unlazy, while the > IPI would be once per process exit. >=20 > So over the life of the process, it might do very many unlazies, adding > up to a total cost far in excess of what the single IPI would've been. Yeah this is the concern, I looked at things that add cost to the idle switch code and it gets hard to justify the scalability improvement when you slow these fundmaental things down even a bit. I still think working on the assumption that IPIs =3D scary expensive=20 might not be correct. An IPI itself is, but you only issue them when=20 you've left a lazy mm on another CPU which just isn't that often. Thanks, Nick