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Thu, 14 Jan 2021 04:09:25 -0800 (PST) Received: from localhost ([124.170.13.62]) by smtp.gmail.com with ESMTPSA id y69sm5286991pfb.64.2021.01.14.04.09.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 04:09:24 -0800 (PST) Date: Thu, 14 Jan 2021 22:09:18 +1000 From: Nicholas Piggin Subject: Re: [PATCH v5 02/21] powerpc/64s: move the last of the page fault handling logic to C To: Christophe Leroy , linuxppc-dev@lists.ozlabs.org References: <20210113073215.516986-1-npiggin@gmail.com> <20210113073215.516986-3-npiggin@gmail.com> <1610592763.5wfbleady7.astroid@bobo.none> In-Reply-To: <1610592763.5wfbleady7.astroid@bobo.none> MIME-Version: 1.0 Message-Id: <1610625340.tqgg2ar1jg.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Nicholas Piggin's message of January 14, 2021 1:24 pm: > Excerpts from Christophe Leroy's message of January 14, 2021 12:12 am: >>=20 >>=20 >> Le 13/01/2021 =C3=A0 08:31, Nicholas Piggin a =C3=A9crit=C2=A0: >>> The page fault handling still has some complex logic particularly aroun= d >>> hash table handling, in asm. Implement this in C instead. >>>=20 >>> Signed-off-by: Nicholas Piggin >>> --- >>> arch/powerpc/include/asm/book3s/64/mmu-hash.h | 1 + >>> arch/powerpc/kernel/exceptions-64s.S | 131 +++--------------= - >>> arch/powerpc/mm/book3s64/hash_utils.c | 77 ++++++---- >>> arch/powerpc/mm/fault.c | 46 ++++-- >>> 4 files changed, 107 insertions(+), 148 deletions(-) >>>=20 >>> diff --git a/arch/powerpc/include/asm/book3s/64/mmu-hash.h b/arch/power= pc/include/asm/book3s/64/mmu-hash.h >>> index 066b1d34c7bc..60a669379aa0 100644 >>> --- a/arch/powerpc/include/asm/book3s/64/mmu-hash.h >>> +++ b/arch/powerpc/include/asm/book3s/64/mmu-hash.h >>> @@ -454,6 +454,7 @@ static inline unsigned long hpt_hash(unsigned long = vpn, >>> #define HPTE_NOHPTE_UPDATE 0x2 >>> #define HPTE_USE_KERNEL_KEY 0x4 >>> =20 >>> +int do_hash_fault(struct pt_regs *regs, unsigned long ea, unsigned lon= g dsisr); >>> extern int __hash_page_4K(unsigned long ea, unsigned long access, >>> unsigned long vsid, pte_t *ptep, unsigned long trap, >>> unsigned long flags, int ssize, int subpage_prot); >>> diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel= /exceptions-64s.S >>> index 6e53f7638737..bcb5e81d2088 100644 >>> --- a/arch/powerpc/kernel/exceptions-64s.S >>> +++ b/arch/powerpc/kernel/exceptions-64s.S >>> @@ -1401,14 +1401,15 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) >>> * >>> * Handling: >>> * - Hash MMU >>> - * Go to do_hash_page first to see if the HPT can be filled from an = entry in >>> - * the Linux page table. Hash faults can hit in kernel mode in a fai= rly >>> + * Go to do_hash_fault, which attempts to fill the HPT from an entry= in the >>> + * Linux page table. Hash faults can hit in kernel mode in a fairly >>> * arbitrary state (e.g., interrupts disabled, locks held) when acc= essing >>> * "non-bolted" regions, e.g., vmalloc space. However these should = always be >>> - * backed by Linux page tables. >>> + * backed by Linux page table entries. >>> * >>> - * If none is found, do a Linux page fault. Linux page faults can ha= ppen in >>> - * kernel mode due to user copy operations of course. >>> + * If no entry is found the Linux page fault handler is invoked (by >>> + * do_hash_fault). Linux page faults can happen in kernel mode due t= o user >>> + * copy operations of course. >>> * >>> * KVM: The KVM HDSI handler may perform a load with MSR[DR]=3D1 in= guest >>> * MMU context, which may cause a DSI in the host, which must go to= the >>> @@ -1439,13 +1440,17 @@ EXC_COMMON_BEGIN(data_access_common) >>> GEN_COMMON data_access >>> ld r4,_DAR(r1) >>> ld r5,_DSISR(r1) >>=20 >> We have DSISR here. I think the dispatch between page fault or do_break(= ) should be done here: >> - It would be more similar to other arches >=20 > Other sub-archs? >=20 >> - Would avoid doing it also in instruction fault >=20 > True but it's hidden under an unlikely branch so won't really help=20 > instruction fault. >=20 >> - Would avoid that -1 return which looks more like a hack. >=20 > I don't really see it as a hack, we return a code to asm caller to > direct whether to restore registers or not, we alrady have this > pattern. >=20 > (I'm hoping all that might be go away one day by conrolling NV > regs from C if we can get good code generation but even if not we > still have it in the interrupt returns). >=20 > That said I will give it a try here. At very least it might be a > better intermediate step. Ah yes, this way doesn't work well for later patches because you end e.g., with the do_break call having to call the interrupt handler wrappers again when they actually expect to be in the asm entry state (e.g., irq soft-mask state) when called, and return via interrupt_return after the exit wrapper runs (which 64s uses to implement better context tracking for example). That could possibly be hacked up to deal with multiple interrupt=20 wrappers per interrupt, but I'd rather not go backwards. That does leave the other sub archs as having this issue, but they don't=20 do so much in their handlers. 32 doesn't have soft-mask or context=20 tracking to deal with for example. We will need to fix this up though=20 and unify things more. Thanks, Nick