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Wed, 03 Feb 2021 06:55:43 +0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 1136tesF33161582 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 3 Feb 2021 06:55:40 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 388474C044; Wed, 3 Feb 2021 06:55:40 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DE6B64C04E; Wed, 3 Feb 2021 06:55:38 +0000 (GMT) Received: from localhost.localdomain.localdomain (unknown [9.79.224.72]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 3 Feb 2021 06:55:38 +0000 (GMT) From: Athira Rajeev To: mpe@ellerman.id.au, acme@kernel.org, jolsa@kernel.org Subject: [PATCH 0/3] powerpc/perf: Add Performance Monitor Counters to extended regs Date: Wed, 3 Feb 2021 01:55:34 -0500 Message-Id: <1612335337-1888-1-git-send-email-atrajeev@linux.vnet.ibm.com> X-Mailer: git-send-email 1.8.3.1 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.737 definitions=2021-02-03_01:2021-02-02, 2021-02-03 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 mlxlogscore=841 priorityscore=1501 bulkscore=0 suspectscore=0 malwarescore=0 impostorscore=0 phishscore=0 spamscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2102030035 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kjain@linux.ibm.com, maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Patch set to add Performance Monitor Counter SPR's as part of extended regs in powerpc. Patch 1/3 saves the PMC values in the perf interrupt handler as part of per-cpu array. Patch 2/3 adds PMC1 to PMC6 as part of the extended regs mask. Patch 3/3 includes perf tools side changes to add PMC1 to PMC6 to sample_reg_mask to use with -I? option. Athira Rajeev (3): powerpc/perf: Include PMCs as part of per-cpu cpuhw_events struct powerpc/perf: Expose Performance Monitor Counter SPR's as part of extended regs tools/perf: Add perf tools support to expose Performance Monitor Counter SPRs as part of extended regs arch/powerpc/include/asm/perf_event.h | 2 ++ arch/powerpc/include/uapi/asm/perf_regs.h | 28 +++++++++++++++++++------ arch/powerpc/perf/core-book3s.c | 28 +++++++++++++++++++------ arch/powerpc/perf/perf_regs.c | 13 ++++-------- tools/arch/powerpc/include/uapi/asm/perf_regs.h | 28 +++++++++++++++++++------ tools/perf/arch/powerpc/include/perf_regs.h | 6 ++++++ tools/perf/arch/powerpc/util/perf_regs.c | 6 ++++++ 7 files changed, 84 insertions(+), 27 deletions(-) -- 1.8.3.1