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[60.242.11.44]) by smtp.gmail.com with ESMTPSA id v31sm6313489pgl.76.2021.02.04.03.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Feb 2021 03:31:35 -0800 (PST) Date: Thu, 04 Feb 2021 21:31:27 +1000 From: Nicholas Piggin Subject: Re: [PATCH v7 39/42] powerpc: move NMI entry/exit code into wrapper To: linuxppc-dev@lists.ozlabs.org, Michael Ellerman References: <20210130130852.2952424-1-npiggin@gmail.com> <20210130130852.2952424-40-npiggin@gmail.com> <87k0rop29e.fsf@mpe.ellerman.id.au> In-Reply-To: <87k0rop29e.fsf@mpe.ellerman.id.au> MIME-Version: 1.0 Message-Id: <1612438069.44myr3nzfs.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Athira Rajeev Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Michael Ellerman's message of February 4, 2021 8:15 pm: > Nicholas Piggin writes: >> This moves the common NMI entry and exit code into the interrupt handler >> wrappers. >> >> This changes the behaviour of soft-NMI (watchdog) and HMI interrupts, an= d >> also MCE interrupts on 64e, by adding missing parts of the NMI entry to >> them. >> >> Signed-off-by: Nicholas Piggin >> --- >> arch/powerpc/include/asm/interrupt.h | 28 ++++++++++++++++++++++ >> arch/powerpc/kernel/mce.c | 11 --------- >> arch/powerpc/kernel/traps.c | 35 +++++----------------------- >> arch/powerpc/kernel/watchdog.c | 10 ++++---- >> 4 files changed, 38 insertions(+), 46 deletions(-) >=20 > This is unhappy when injecting SLB multi-hits: >=20 > root@p86-2:~# echo PPC_SLB_MULTIHIT > /sys/kernel/debug/provoke-crash/D= IRECT > [ 312.496026][ T1344] kernel BUG at arch/powerpc/include/asm/interrupt= .h:152! > [ 312.496037][ T1344] Oops: Exception in kernel mode, sig: 5 [#1] > [ 312.496045][ T1344] LE PAGE_SIZE=3D64K MMU=3DHash SMP NR_CPUS=3D2048= NUMA pSeries pseries hash. Blast! > 147 static inline void interrupt_nmi_exit_prepare(struct pt_regs *regs, s= truct interrupt_nmi_state *state) > 148 { > 149 if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) || > 150 !firmware_has_feature(FW_FEATURE_LPAR) || > 151 radix_enabled() || (mfmsr() & MSR_DR)) > 152 nmi_exit(); >=20 >=20 > So presumably it's: >=20 > #define __nmi_exit() \ > do { \ > BUG_ON(!in_nmi()); \ Yes that would be it, pseries machine check enables MMU half way through=20 so only one side of this triggers. The MSR_DR check is supposed to catch the other NMIs that run with MMU=20 on (perf, watchdog, etc). Suppose it could test TRAP(regs) explicitly although I wonder if we should also do this to keep things balanced diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/= pseries/ras.c index 149cec2212e6..f57ca0c570be 100644 --- a/arch/powerpc/platforms/pseries/ras.c +++ b/arch/powerpc/platforms/pseries/ras.c @@ -719,6 +719,7 @@ static int mce_handle_err_virtmode(struct pt_regs *regs= , =20 static int mce_handle_error(struct pt_regs *regs, struct rtas_error_log *e= rrp) { + unsigned long msr; struct pseries_errorlog *pseries_log; struct pseries_mc_errorlog *mce_log =3D NULL; int disposition =3D rtas_error_disposition(errp); @@ -747,9 +748,12 @@ static int mce_handle_error(struct pt_regs *regs, stru= ct rtas_error_log *errp) * SLB multihit is done by now. */ out: - mtmsr(mfmsr() | MSR_IR | MSR_DR); + msr =3D mfmsr(); + mtmsr(msr | MSR_IR | MSR_DR); disposition =3D mce_handle_err_virtmode(regs, errp, mce_log, disposition); + mtmsr(msr); + return disposition; } =20