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Mon, 08 Feb 2021 17:14:29 -0800 (PST) Received: from localhost ([220.240.226.199]) by smtp.gmail.com with ESMTPSA id y9sm6455496pfr.192.2021.02.08.17.14.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Feb 2021 17:14:29 -0800 (PST) Date: Tue, 09 Feb 2021 11:14:24 +1000 From: Nicholas Piggin Subject: Re: [PATCH v5 06/22] powerpc/irq: Rework helpers that manipulate MSR[EE/RI] To: Benjamin Herrenschmidt , Christophe Leroy , Michael Ellerman , msuchanek@suse.de, Paul Mackerras References: <0e290372a0e7dc2ae657b4a01aec85f8de7fdf77.1612796617.git.christophe.leroy@csgroup.eu> In-Reply-To: <0e290372a0e7dc2ae657b4a01aec85f8de7fdf77.1612796617.git.christophe.leroy@csgroup.eu> MIME-Version: 1.0 Message-Id: <1612833191.rod6qskvzc.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Christophe Leroy's message of February 9, 2021 1:10 am: > In preparation of porting PPC32 to C syscall entry/exit, > rewrite the following helpers as static inline functions and > add support for PPC32 in them: > __hard_irq_enable() > __hard_irq_disable() > __hard_EE_RI_disable() > __hard_RI_enable() >=20 > Then use them in PPC32 version of arch_local_irq_disable() > and arch_local_irq_enable() to avoid code duplication. >=20 Reviewed-by: Nicholas Piggin > Signed-off-by: Christophe Leroy > --- > arch/powerpc/include/asm/hw_irq.h | 75 +++++++++++++++++++++---------- > arch/powerpc/include/asm/reg.h | 1 + > 2 files changed, 52 insertions(+), 24 deletions(-) >=20 > diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm= /hw_irq.h > index ed0c3b049dfd..4739f61e632c 100644 > --- a/arch/powerpc/include/asm/hw_irq.h > +++ b/arch/powerpc/include/asm/hw_irq.h > @@ -50,6 +50,55 @@ > =20 > #ifndef __ASSEMBLY__ > =20 > +static inline void __hard_irq_enable(void) > +{ > + if (IS_ENABLED(CONFIG_BOOKE) || IS_ENABLED(CONFIG_40x)) > + wrtee(MSR_EE); > + else if (IS_ENABLED(CONFIG_PPC_8xx)) > + wrtspr(SPRN_EIE); > + else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) > + __mtmsrd(MSR_EE | MSR_RI, 1); > + else > + mtmsr(mfmsr() | MSR_EE); > +} > + > +static inline void __hard_irq_disable(void) > +{ > + if (IS_ENABLED(CONFIG_BOOKE) || IS_ENABLED(CONFIG_40x)) > + wrtee(0); > + else if (IS_ENABLED(CONFIG_PPC_8xx)) > + wrtspr(SPRN_EID); > + else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) > + __mtmsrd(MSR_RI, 1); > + else > + mtmsr(mfmsr() & ~MSR_EE); > +} > + > +static inline void __hard_EE_RI_disable(void) > +{ > + if (IS_ENABLED(CONFIG_BOOKE) || IS_ENABLED(CONFIG_40x)) > + wrtee(0); > + else if (IS_ENABLED(CONFIG_PPC_8xx)) > + wrtspr(SPRN_NRI); > + else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) > + __mtmsrd(0, 1); > + else > + mtmsr(mfmsr() & ~(MSR_EE | MSR_RI)); > +} > + > +static inline void __hard_RI_enable(void) > +{ > + if (IS_ENABLED(CONFIG_BOOKE) || IS_ENABLED(CONFIG_40x)) > + return; > + > + if (IS_ENABLED(CONFIG_PPC_8xx)) > + wrtspr(SPRN_EID); > + else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) > + __mtmsrd(MSR_RI, 1); > + else > + mtmsr(mfmsr() | MSR_RI); > +} > + > #ifdef CONFIG_PPC64 > #include > =20 > @@ -212,18 +261,6 @@ static inline bool arch_irqs_disabled(void) > =20 > #endif /* CONFIG_PPC_BOOK3S */ > =20 > -#ifdef CONFIG_PPC_BOOK3E > -#define __hard_irq_enable() wrtee(MSR_EE) > -#define __hard_irq_disable() wrtee(0) > -#define __hard_EE_RI_disable() wrtee(0) > -#define __hard_RI_enable() do { } while (0) > -#else > -#define __hard_irq_enable() __mtmsrd(MSR_EE|MSR_RI, 1) > -#define __hard_irq_disable() __mtmsrd(MSR_RI, 1) > -#define __hard_EE_RI_disable() __mtmsrd(0, 1) > -#define __hard_RI_enable() __mtmsrd(MSR_RI, 1) > -#endif > - > #define hard_irq_disable() do { \ > unsigned long flags; \ > __hard_irq_disable(); \ > @@ -322,22 +359,12 @@ static inline unsigned long arch_local_irq_save(voi= d) > =20 > static inline void arch_local_irq_disable(void) > { > - if (IS_ENABLED(CONFIG_BOOKE)) > - wrtee(0); > - else if (IS_ENABLED(CONFIG_PPC_8xx)) > - wrtspr(SPRN_EID); > - else > - mtmsr(mfmsr() & ~MSR_EE); > + __hard_irq_disable(); > } > =20 > static inline void arch_local_irq_enable(void) > { > - if (IS_ENABLED(CONFIG_BOOKE)) > - wrtee(MSR_EE); > - else if (IS_ENABLED(CONFIG_PPC_8xx)) > - wrtspr(SPRN_EIE); > - else > - mtmsr(mfmsr() | MSR_EE); > + __hard_irq_enable(); > } > =20 > static inline bool arch_irqs_disabled_flags(unsigned long flags) > diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/re= g.h > index c5a3e856191c..bc4305ba00d0 100644 > --- a/arch/powerpc/include/asm/reg.h > +++ b/arch/powerpc/include/asm/reg.h > @@ -1375,6 +1375,7 @@ > #define mtmsr(v) asm volatile("mtmsr %0" : \ > : "r" ((unsigned long)(v)) \ > : "memory") > +#define __mtmsrd(v, l) BUILD_BUG() > #define __MTMSR "mtmsr" > #endif > =20 > --=20 > 2.25.0 >=20 >=20