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[14.201.150.91]) by smtp.gmail.com with ESMTPSA id u18sm2000287pjn.18.2021.02.10.03.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 03:45:20 -0800 (PST) Date: Wed, 10 Feb 2021 21:45:14 +1000 From: Nicholas Piggin Subject: Re: interrupt_exit_kernel_prepare() on booke/32 has a useless 'mfmsr' and two 'wrteei 0' To: Christophe Leroy , "linuxppc-dev@lists.ozlabs.org" References: In-Reply-To: MIME-Version: 1.0 Message-Id: <1612956047.1868npztxj.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Christophe Leroy's message of February 10, 2021 7:21 pm: > 44x/bamboo_defconfig >=20 > For the mfmsr, that's because mfmsr is defined as 'asm volatile'. Is that= correct ? Reading MSR=20 > doesn't have any side effects as far as I know, should we remove the vola= tile ? Well I'm not really sure. It depends on the MSR value, so it must not=20 assume it's unchanging. If you just have asm ("mfmsr %0" : "=3Dr"(msr)) then that's wrong because=20 it will omit the second mfmsr in a mfmsr() ; mtmsr() ; mfmsr() sequence. Adding a "memory" clobber there makes gcc produce the second mfmsr, but=20 I don't know if that's really the right thing to do. >=20 > For the wrteei, that's because we are calling __hard_EE_RI_disable() afte= r local_irq_save(). On=20 > booke those two fonctions do exactly the same because RI doesn't exist. C= ould we replace that by a=20 > __hard_RI_disable() that would be a nop on booke ? Not on 64-bit because local_irq_disable() doesn't disable EE there. You could have something like __hard_EE_RI_disable_irqoff() that is to=20 be called only in irq disabled region. But is that just adding too much=20 complexity to try to keep 32 and 64 bit unified? Maybe just making different code paths for 32 and 64 would be best.=20 32-bit seems fairly simple if (!arch_irq_disabled_regs(regs)) { /* Returning to a kernel context with local irqs enabled. *= / WARN_ON_ONCE(!(regs->msr & MSR_EE)); local_irq_disable(); if (IS_ENABLED(CONFIG_PREEMPT)) { /* Return to preemptible kernel context */ if (unlikely(*ti_flagsp & _TIF_NEED_RESCHED)) { if (preempt_count() =3D=3D 0) preempt_schedule_irq(); } } trace_hardirqs_on(); __hard_RI_disable(); } else { __hard_EE_RI_disable(); } You could get rid of that entirely if no preempt or irq tracing and just have __hard_EE_RI_disable even AFAIKS. Thanks, Nick