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[14.201.150.91]) by smtp.gmail.com with ESMTPSA id w3sm7624044pjb.2.2021.02.19.00.03.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Feb 2021 00:03:17 -0800 (PST) Date: Fri, 19 Feb 2021 18:03:12 +1000 From: Nicholas Piggin Subject: Re: [RFC PATCH 1/9] KVM: PPC: Book3S 64: move KVM interrupt entry to a common entry point To: Daniel Axtens , kvm-ppc@vger.kernel.org References: <20210202030313.3509446-1-npiggin@gmail.com> <20210202030313.3509446-2-npiggin@gmail.com> <87o8ggab50.fsf@linkitivity.dja.id.au> In-Reply-To: <87o8ggab50.fsf@linkitivity.dja.id.au> MIME-Version: 1.0 Message-Id: <1613721408.9e7tf7vuqz.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Daniel Axtens's message of February 19, 2021 3:18 pm: > Hi Nick, >=20 >> +++ b/arch/powerpc/kvm/book3s_64_entry.S >> @@ -0,0 +1,34 @@ >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +/* >> + * We come here from the first-level interrupt handlers. >> + */ >> +.global kvmppc_interrupt >> +.balign IFETCH_ALIGN_BYTES >> +kvmppc_interrupt: >> + /* >> + * Register contents: >=20 > Clearly r9 contains some data at this point, and I think it's guest r9 > because of what you say later on in > book3s_hv_rmhandlers.S::kvmppc_interrupt_hv. Is that right? Yes I hope so. > Should that > be documented in this comment as well? Normally it can be assumed the registers not explicitly enumerated would=20 be unchanged from the interrupted context, so they would all contain=20 guest values. I added the R9 contents comment later because I changed it later. >=20 >> + * R12 =3D (guest CR << 32) | interrupt vector >> + * R13 =3D PACA >> + * guest R12 saved in shadow VCPU SCRATCH0 >> + * guest R13 saved in SPRN_SCRATCH0 >> + */ >> +#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE >> + std r9, HSTATE_SCRATCH2(r13) >> + lbz r9, HSTATE_IN_GUEST(r13) >> + cmpwi r9, KVM_GUEST_MODE_HOST_HV >> + beq kvmppc_bad_host_intr >> +#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE >> + cmpwi r9, KVM_GUEST_MODE_GUEST >> + ld r9, HSTATE_SCRATCH2(r13) >> + beq kvmppc_interrupt_pr >> +#endif >> + b kvmppc_interrupt_hv >> +#else >> + b kvmppc_interrupt_pr >> +#endif >=20 > Apart from that I had a look and convinced myself that the code will > behave the same as before. On that basis: >=20 > Reviewed-by: Daniel Axtens >=20 > Kind regards, > Daniel Thanks, Nick >=20