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[58.6.239.121]) by smtp.gmail.com with ESMTPSA id gm10sm1834749pjb.4.2021.03.16.00.11.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 00:11:49 -0700 (PDT) Date: Tue, 16 Mar 2021 17:11:42 +1000 From: Nicholas Piggin Subject: Re: [PATCH 10/10] powerpc: move norestart trap flag to bit 0 To: Christophe Leroy , linuxppc-dev@lists.ozlabs.org References: <20210315031716.3940350-1-npiggin@gmail.com> <20210315031716.3940350-11-npiggin@gmail.com> <99f15df0-dc86-4601-066f-a6c067ece8bf@csgroup.eu> In-Reply-To: <99f15df0-dc86-4601-066f-a6c067ece8bf@csgroup.eu> MIME-Version: 1.0 Message-Id: <1615878424.0gp943h7l3.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Scott Wood Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Christophe Leroy's message of March 15, 2021 6:14 pm: >=20 >=20 > Le 15/03/2021 =C3=A0 04:17, Nicholas Piggin a =C3=A9crit=C2=A0: >> Compact the trap flags down to use the low 4 bits of regs.trap. >>=20 >> A few 64e interrupt trap numbers set bit 4. Although they tended to be >> trivial so it wasn't a real problem[1], it is not the right thing to do, >> and confusing. >>=20 >> [*] E.g., 0x310 hypercall goes to unknown_exception, which prints >> regs->trap directly so 0x310 will appear fine, and only the syscall >> interrupt will test norestart, so it won't be confused by 0x310. >>=20 >> Signed-off-by: Nicholas Piggin >> --- >> arch/powerpc/include/asm/ptrace.h | 14 ++++++++++---- >> 1 file changed, 10 insertions(+), 4 deletions(-) >>=20 >> diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/as= m/ptrace.h >> index 91194fdd5d01..6a04abfe5eb6 100644 >> --- a/arch/powerpc/include/asm/ptrace.h >> +++ b/arch/powerpc/include/asm/ptrace.h >> @@ -185,15 +185,21 @@ static inline void regs_set_return_value(struct pt= _regs *regs, unsigned long rc) >> #define current_pt_regs() \ >> ((struct pt_regs *)((unsigned long)task_stack_page(current) + THREAD_= SIZE) - 1) >> =20 >> +/* >> + * The 4 low bits (0xf) are available as flags to overload the trap wor= d, >> + * because interrupt vectors have minimum alignment of 0x10. TRAP_FLAGS= _MASK >> + * must cover the bits used as flags, including bit 0 which is used as = the >> + * "norestart" bit. >> + */ >> #ifdef __powerpc64__ >> -#define TRAP_FLAGS_MASK 0x10 >> +#define TRAP_FLAGS_MASK 0x1 >> #define TRAP(regs) ((regs)->trap & ~TRAP_FLAGS_MASK) >> #else >> /* >> * On 4xx we use bit 1 in the trap word to indicate whether the except= ion >> * is a critical exception (1 means it is). >> */ >> -#define TRAP_FLAGS_MASK 0x1E >> +#define TRAP_FLAGS_MASK 0xf >=20 > Could we set 0xf for all and remove the ifdef __powerpc64__ ? I like that it documents the bit number allocation so I prefer to leave=20 it, but TRAP() does not have to be defined twice at least. >=20 >> #define TRAP(regs) ((regs)->trap & ~TRAP_FLAGS_MASK) >> #define IS_CRITICAL_EXC(regs) (((regs)->trap & 2) !=3D 0) >> #define IS_MCHECK_EXC(regs) (((regs)->trap & 4) !=3D 0) >> @@ -222,12 +228,12 @@ static inline bool trap_is_syscall(struct pt_regs = *regs) >> =20 >> static inline bool trap_norestart(struct pt_regs *regs) >> { >> - return regs->trap & 0x10; >> + return regs->trap & 0x1; >> } >> =20 >> static inline void set_trap_norestart(struct pt_regs *regs) >> { >> - regs->trap |=3D 0x10; >> + regs->trap |=3D 0x1; >> } >> =20 >> #define arch_has_single_step() (1) >>=20 >=20 > While we are playing with ->trap, in mm/book3s64/hash_utils.c there is an= if (regs->trap =3D=3D 0x400).=20 > Should be TRAP(regs) =3D=3D 0x400 ? Yes I would say so, if you want to do a patch you can add Acked-by: Nicholas Piggin Otherwise I can do it. Thanks, Nick