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[58.6.239.121]) by smtp.gmail.com with ESMTPSA id r186sm15873865pfr.124.2021.03.16.01.11.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 01:11:48 -0700 (PDT) Date: Tue, 16 Mar 2021 18:11:42 +1000 From: Nicholas Piggin Subject: Re: [PATCH] powerpc/64s: power4 nap fixup in C To: Christophe Leroy , linuxppc-dev@lists.ozlabs.org References: <20210312012044.3660743-1-npiggin@gmail.com> <6ab2073b-dd10-ef2c-375d-1300f071ae1a@csgroup.eu> In-Reply-To: <6ab2073b-dd10-ef2c-375d-1300f071ae1a@csgroup.eu> MIME-Version: 1.0 Message-Id: <1615882185.2o1zpw54nt.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Christophe Leroy's message of March 16, 2021 5:16 pm: >=20 >=20 > Le 12/03/2021 =C3=A0 02:20, Nicholas Piggin a =C3=A9crit=C2=A0: >> There is no need for this to be in asm, use the new intrrupt entry wrapp= er. >>=20 >> Signed-off-by: Nicholas Piggin >> --- >> Hopefully this works on a real G5 now, but I couldn't reproduce the >> problem with QEMU. >>=20 >> Thanks, >> Nick >>=20 >> arch/powerpc/include/asm/interrupt.h | 19 +++++++++++ >> arch/powerpc/include/asm/processor.h | 1 + >> arch/powerpc/include/asm/thread_info.h | 6 ++++ >> arch/powerpc/kernel/exceptions-64s.S | 45 -------------------------- >> arch/powerpc/kernel/idle_book3s.S | 4 +++ >> 5 files changed, 30 insertions(+), 45 deletions(-) >>=20 >> diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include= /asm/interrupt.h >> index aedfba29e43a..ef015d3b5e39 100644 >> --- a/arch/powerpc/include/asm/interrupt.h >> +++ b/arch/powerpc/include/asm/interrupt.h >> @@ -9,6 +9,17 @@ >> #include >> #include >> =20 >> +static inline void nap_adjust_return(struct pt_regs *regs) >> +{ >> +#ifdef CONFIG_PPC_970_NAP >> + if (unlikely(test_thread_local_flags(_TLF_NAPPING))) { >> + /* Can avoid a test-and-clear because NMIs do not call this */ >> + clear_thread_local_flags(_TLF_NAPPING); >> + regs->nip =3D (unsigned long)power4_idle_nap_return; >=20 > Why don't you do regs->nip =3D regs->link like PPC32 instead of going via= an intermediate symbol that=20 > does nothing else than branching to LR ? It is supposed to keep the return branch predictor balanced. I don't know if these CPUs have one, if it gets lost during nap, or if=20 nap latency is so high it really doesn't matter. But I think it is good practice to make a habit of keeping things balanced. Thanks, Nick