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[60.242.147.73]) by smtp.gmail.com with ESMTPSA id p14sm14757925pgb.2.2021.06.14.18.12.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Jun 2021 18:12:25 -0700 (PDT) Date: Tue, 15 Jun 2021 11:12:20 +1000 From: Nicholas Piggin Subject: Re: [PATCH 03/11] powerpc/radix: Add support for microwatt's PRTBL SPR To: linuxppc-dev@ozlabs.org, Paul Mackerras References: In-Reply-To: MIME-Version: 1.0 Message-Id: <1623719194.0n4wcgijzy.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Paul Mackerras's message of June 15, 2021 8:59 am: > Microwatt currently doesn't implement hypervisor mode and therefore > doesn't implement the partition table. It does implement the process > table and radix page table walks. >=20 > This adds code to write the base address of the process table to the > PRTBL SPR, Is there a particular reason you haven't called it PRTCR or similar to=20 match PTCR? > which has been assigned SPR 720 for now, as that is in the > range of SPR numbers assigned for experimental use. PRTBL is only > written when we have neither the FW_FEATURE_LPAR feature nor the > CPU_FTR_HVMODE feature. Seems like reasonable architecture for a non-HV platform. Could it have a comment to say it's not architected, and a microwatt ifdef until that changes? The patch also does avoid touching LPCR or initing amor... Thanks, Nick >=20 > Signed-off-by: Paul Mackerras > --- > arch/powerpc/include/asm/reg.h | 1 + > arch/powerpc/mm/book3s64/radix_pgtable.c | 13 +++++++++---- > 2 files changed, 10 insertions(+), 4 deletions(-) >=20 > diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/re= g.h > index da103e92c112..3200a2522d6c 100644 > --- a/arch/powerpc/include/asm/reg.h > +++ b/arch/powerpc/include/asm/reg.h > @@ -729,6 +729,7 @@ > #endif > #define SPRN_TIR 0x1BE /* Thread Identification Register */ > #define SPRN_PTCR 0x1D0 /* Partition table control Register */ > +#define SPRN_PRTBL 0x2D0 /* Process table pointer */ > #define SPRN_PSPB 0x09F /* Problem State Priority Boost reg */ > #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ > #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ > diff --git a/arch/powerpc/mm/book3s64/radix_pgtable.c b/arch/powerpc/mm/b= ook3s64/radix_pgtable.c > index 98f0b243c1ab..6595859173a7 100644 > --- a/arch/powerpc/mm/book3s64/radix_pgtable.c > +++ b/arch/powerpc/mm/book3s64/radix_pgtable.c > @@ -646,10 +646,15 @@ void __init radix__early_init_mmu(void) > radix_init_pgtable(); > =20 > if (!firmware_has_feature(FW_FEATURE_LPAR)) { > - lpcr =3D mfspr(SPRN_LPCR); > - mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); > - radix_init_partition_table(); > - radix_init_amor(); > + if (cpu_has_feature(CPU_FTR_HVMODE)) { > + lpcr =3D mfspr(SPRN_LPCR); > + mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR); > + radix_init_partition_table(); > + radix_init_amor(); > + } else { > + mtspr(SPRN_PRTBL, (__pa(process_tb) | > + (PRTB_SIZE_SHIFT - 12))); > + } > } else { > radix_init_pseries(); > } > --=20 > 2.31.1 >=20 >=20