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Thu, 01 Jul 2021 17:27:07 -0700 (PDT) Received: from localhost ([118.209.250.144]) by smtp.gmail.com with ESMTPSA id e1sm1228899pfd.16.2021.07.01.17.27.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jul 2021 17:27:06 -0700 (PDT) Date: Fri, 02 Jul 2021 10:27:01 +1000 From: Nicholas Piggin Subject: Re: [RFC PATCH 10/43] powerpc/64s: Always set PMU control registers to frozen/disabled when not in use To: kvm-ppc@vger.kernel.org, Madhavan Srinivasan References: <20210622105736.633352-1-npiggin@gmail.com> <20210622105736.633352-11-npiggin@gmail.com> In-Reply-To: MIME-Version: 1.0 Message-Id: <1625185125.n8jy7yqojr.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Madhavan Srinivasan's message of July 1, 2021 11:17 pm: >=20 > On 6/22/21 4:27 PM, Nicholas Piggin wrote: >> KVM PMU management code looks for particular frozen/disabled bits in >> the PMU registers so it knows whether it must clear them when coming >> out of a guest or not. Setting this up helps KVM make these optimisation= s >> without getting confused. Longer term the better approach might be to >> move guest/host PMU switching to the perf subsystem. >> >> Signed-off-by: Nicholas Piggin >> --- >> arch/powerpc/kernel/cpu_setup_power.c | 4 ++-- >> arch/powerpc/kernel/dt_cpu_ftrs.c | 6 +++--- >> arch/powerpc/kvm/book3s_hv.c | 5 +++++ >> arch/powerpc/perf/core-book3s.c | 7 +++++++ >> 4 files changed, 17 insertions(+), 5 deletions(-) >> >> diff --git a/arch/powerpc/kernel/cpu_setup_power.c b/arch/powerpc/kernel= /cpu_setup_power.c >> index a29dc8326622..3dc61e203f37 100644 >> --- a/arch/powerpc/kernel/cpu_setup_power.c >> +++ b/arch/powerpc/kernel/cpu_setup_power.c >> @@ -109,7 +109,7 @@ static void init_PMU_HV_ISA207(void) >> static void init_PMU(void) >> { >> mtspr(SPRN_MMCRA, 0); >> - mtspr(SPRN_MMCR0, 0); >> + mtspr(SPRN_MMCR0, MMCR0_FC); >=20 > Sticky point here is, currently if not frozen, pmc5/6 will > keep countering. And not freezing them at boot is quiet useful > sometime, like say when running in a simulation where we could calculate > approx CPIs for micro benchmarks without perf subsystem. You even can't use the sysfs files in this sim environment? In that case what if we added a boot option that could set some things up? In that=20 case possibly you could even gather some more types of events too. Thanks, Nick