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[14.203.186.173]) by smtp.gmail.com with ESMTPSA id j23sm3103816pfd.12.2021.07.08.05.57.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jul 2021 05:57:02 -0700 (PDT) Date: Thu, 08 Jul 2021 22:56:57 +1000 From: Nicholas Piggin Subject: Re: [PATCH] powerpc/perf: Fix cycles/instructions as PM_CYC/PM_INST_CMPL in power10 To: Athira Rajeev , mpe@ellerman.id.au References: <1625639981-1424-1-git-send-email-atrajeev@linux.vnet.ibm.com> In-Reply-To: <1625639981-1424-1-git-send-email-atrajeev@linux.vnet.ibm.com> MIME-Version: 1.0 Message-Id: <1625748771.problnjoqz.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Athira Rajeev's message of July 7, 2021 4:39 pm: > From: Athira Rajeev >=20 > Power10 performance monitoring unit (PMU) driver uses performance > monitor counter 5 (PMC5) and performance monitor counter 6 (PMC6) > for counting instructions and cycles. Event used for cycles is > PM_RUN_CYC and instructions is PM_RUN_INST_CMPL. But counting of these > events in wait state is controlled by the CC56RUN bit setting in > Monitor Mode Control Register0 (MMCR0). If the CC56RUN bit is not > set, PMC5/6 will not count when CTRL[RUN] is zero. What's the acutal bug here, can you explain a bit more? I thought PM_RUN_CYC is supposed to be gated by the runlatch. POWER9 code looks similar, it doesn't have the same problem? Thanks, Nick >=20 > Patch sets the CC56RUN bit in MMCR0 for power10 which makes PMC5 and > PMC6 count instructions and cycles regardless of the run bit. With this > change, these events are also now renamed to PM_CYC and PM_INST_CMPL > rather than PM_RUN_CYC and PM_RUN_INST_CMPL. >=20 > Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring suppor= t") > Signed-off-by: Athira Rajeev > Reviewed-by: Madhavan Srinivasan > --- > Notes on testing done for this change: > Tested this patch change with a kernel module that > turns off and turns on the runlatch. kernel module also > reads the counter values for PMC5 and PMC6 during the > period when runlatch is off. > - Started PMU counters via "perf stat" and loaded the > test module. > - Checked the counter values captured from module during > the runlatch off period. > - Verified that counters were frozen without the patch and > with the patch, observed counters were incrementing. >=20 > arch/powerpc/perf/power10-events-list.h | 8 +++--- > arch/powerpc/perf/power10-pmu.c | 44 +++++++++++++++++++++++----= ------ > 2 files changed, 35 insertions(+), 17 deletions(-) >=20 > diff --git a/arch/powerpc/perf/power10-events-list.h b/arch/powerpc/perf/= power10-events-list.h > index 93be719..564f1409 100644 > --- a/arch/powerpc/perf/power10-events-list.h > +++ b/arch/powerpc/perf/power10-events-list.h > @@ -9,10 +9,10 @@ > /* > * Power10 event codes. > */ > -EVENT(PM_RUN_CYC, 0x600f4); > +EVENT(PM_CYC, 0x600f4); > EVENT(PM_DISP_STALL_CYC, 0x100f8); > EVENT(PM_EXEC_STALL, 0x30008); > -EVENT(PM_RUN_INST_CMPL, 0x500fa); > +EVENT(PM_INST_CMPL, 0x500fa); > EVENT(PM_BR_CMPL, 0x4d05e); > EVENT(PM_BR_MPRED_CMPL, 0x400f6); > EVENT(PM_BR_FIN, 0x2f04a); > @@ -50,8 +50,8 @@ > /* ITLB Reloaded */ > EVENT(PM_ITLB_MISS, 0x400fc); > =20 > -EVENT(PM_RUN_CYC_ALT, 0x0001e); > -EVENT(PM_RUN_INST_CMPL_ALT, 0x00002); > +EVENT(PM_CYC_ALT, 0x0001e); > +EVENT(PM_INST_CMPL_ALT, 0x00002); > =20 > /* > * Memory Access Events > diff --git a/arch/powerpc/perf/power10-pmu.c b/arch/powerpc/perf/power10-= pmu.c > index f9d64c6..9dd75f3 100644 > --- a/arch/powerpc/perf/power10-pmu.c > +++ b/arch/powerpc/perf/power10-pmu.c > @@ -91,8 +91,8 @@ > =20 > /* Table of alternatives, sorted by column 0 */ > static const unsigned int power10_event_alternatives[][MAX_ALT] =3D { > - { PM_RUN_CYC_ALT, PM_RUN_CYC }, > - { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL }, > + { PM_CYC_ALT, PM_CYC }, > + { PM_INST_CMPL_ALT, PM_INST_CMPL }, > }; > =20 > static int power10_get_alternatives(u64 event, unsigned int flags, u64 a= lt[]) > @@ -118,8 +118,8 @@ static int power10_check_attr_config(struct perf_even= t *ev) > return 0; > } > =20 > -GENERIC_EVENT_ATTR(cpu-cycles, PM_RUN_CYC); > -GENERIC_EVENT_ATTR(instructions, PM_RUN_INST_CMPL); > +GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); > +GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL); > GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL); > GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL); > GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); > @@ -148,8 +148,8 @@ static int power10_check_attr_config(struct perf_even= t *ev) > CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); > =20 > static struct attribute *power10_events_attr_dd1[] =3D { > - GENERIC_EVENT_PTR(PM_RUN_CYC), > - GENERIC_EVENT_PTR(PM_RUN_INST_CMPL), > + GENERIC_EVENT_PTR(PM_CYC), > + GENERIC_EVENT_PTR(PM_INST_CMPL), > GENERIC_EVENT_PTR(PM_BR_CMPL), > GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), > GENERIC_EVENT_PTR(PM_LD_REF_L1), > @@ -173,8 +173,8 @@ static int power10_check_attr_config(struct perf_even= t *ev) > }; > =20 > static struct attribute *power10_events_attr[] =3D { > - GENERIC_EVENT_PTR(PM_RUN_CYC), > - GENERIC_EVENT_PTR(PM_RUN_INST_CMPL), > + GENERIC_EVENT_PTR(PM_CYC), > + GENERIC_EVENT_PTR(PM_INST_CMPL), > GENERIC_EVENT_PTR(PM_BR_FIN), > GENERIC_EVENT_PTR(PM_MPRED_BR_FIN), > GENERIC_EVENT_PTR(PM_LD_REF_L1), > @@ -271,8 +271,8 @@ static int power10_check_attr_config(struct perf_even= t *ev) > }; > =20 > static int power10_generic_events_dd1[] =3D { > - [PERF_COUNT_HW_CPU_CYCLES] =3D PM_RUN_CYC, > - [PERF_COUNT_HW_INSTRUCTIONS] =3D PM_RUN_INST_CMPL, > + [PERF_COUNT_HW_CPU_CYCLES] =3D PM_CYC, > + [PERF_COUNT_HW_INSTRUCTIONS] =3D PM_INST_CMPL, > [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =3D PM_BR_CMPL, > [PERF_COUNT_HW_BRANCH_MISSES] =3D PM_BR_MPRED_CMPL, > [PERF_COUNT_HW_CACHE_REFERENCES] =3D PM_LD_REF_L1, > @@ -280,8 +280,8 @@ static int power10_check_attr_config(struct perf_even= t *ev) > }; > =20 > static int power10_generic_events[] =3D { > - [PERF_COUNT_HW_CPU_CYCLES] =3D PM_RUN_CYC, > - [PERF_COUNT_HW_INSTRUCTIONS] =3D PM_RUN_INST_CMPL, > + [PERF_COUNT_HW_CPU_CYCLES] =3D PM_CYC, > + [PERF_COUNT_HW_INSTRUCTIONS] =3D PM_INST_CMPL, > [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =3D PM_BR_FIN, > [PERF_COUNT_HW_BRANCH_MISSES] =3D PM_MPRED_BR_FIN, > [PERF_COUNT_HW_CACHE_REFERENCES] =3D PM_LD_REF_L1, > @@ -548,6 +548,24 @@ static void power10_config_bhrb(u64 pmu_bhrb_filter) > =20 > #undef C > =20 > +/* > + * Set the MMCR0[CC56RUN] bit to enable counting for > + * PMC5 and PMC6 regardless of the state of CTRL[RUN], > + * so that we can use counters 5 and 6 as PM_INST_CMPL and > + * PM_CYC. > + */ > +static int power10_compute_mmcr(u64 event[], int n_ev, > + unsigned int hwc[], struct mmcr_regs *mmcr, > + struct perf_event *pevents[], u32 flags) > +{ > + int ret; > + > + ret =3D isa207_compute_mmcr(event, n_ev, hwc, mmcr, pevents, flags); > + if (!ret) > + mmcr->mmcr0 |=3D MMCR0_C56RUN; > + return ret; > +} > + > static struct power_pmu power10_pmu =3D { > .name =3D "POWER10", > .n_counter =3D MAX_PMU_COUNTERS, > @@ -555,7 +573,7 @@ static void power10_config_bhrb(u64 pmu_bhrb_filter) > .test_adder =3D ISA207_TEST_ADDER, > .group_constraint_mask =3D CNST_CACHE_PMC4_MASK, > .group_constraint_val =3D CNST_CACHE_PMC4_VAL, > - .compute_mmcr =3D isa207_compute_mmcr, > + .compute_mmcr =3D power10_compute_mmcr, > .config_bhrb =3D power10_config_bhrb, > .bhrb_filter_map =3D power10_bhrb_filter_map, > .get_constraint =3D isa207_get_constraint, > --=20 > 1.8.3.1 >=20 >=20