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Fri, 06 Aug 2021 03:42:11 -0700 (PDT) Received: from localhost ([118.210.97.79]) by smtp.gmail.com with ESMTPSA id g22sm666973pfo.164.2021.08.06.03.42.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Aug 2021 03:42:11 -0700 (PDT) Date: Fri, 06 Aug 2021 20:42:06 +1000 From: Nicholas Piggin Subject: Re: [PATCH v1 16/55] powerpc/64s: Implement PMU override command line option To: Athira Rajeev References: <20210726035036.739609-1-npiggin@gmail.com> <20210726035036.739609-17-npiggin@gmail.com> <4600EC62-5505-4856-AE23-939ED62287B3@linux.vnet.ibm.com> In-Reply-To: <4600EC62-5505-4856-AE23-939ED62287B3@linux.vnet.ibm.com> MIME-Version: 1.0 Message-Id: <1628246339.762vtrxskz.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, kvm-ppc@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Athira Rajeev's message of August 6, 2021 7:28 pm: >=20 >=20 >> On 26-Jul-2021, at 9:19 AM, Nicholas Piggin wrote: >>=20 >> It can be useful in simulators (with very constrained environments) >> to allow some PMCs to run from boot so they can be sampled directly >> by a test harness, rather than having to run perf. >>=20 >> A previous change freezes counters at boot by default, so provide >> a boot time option to un-freeze (plus a bit more flexibility). >>=20 >> Signed-off-by: Nicholas Piggin >> --- >> .../admin-guide/kernel-parameters.txt | 7 ++++ >> arch/powerpc/perf/core-book3s.c | 35 +++++++++++++++++++ >> 2 files changed, 42 insertions(+) >>=20 >> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documenta= tion/admin-guide/kernel-parameters.txt >> index bdb22006f713..96b7d0ebaa40 100644 >> --- a/Documentation/admin-guide/kernel-parameters.txt >> +++ b/Documentation/admin-guide/kernel-parameters.txt >> @@ -4089,6 +4089,13 @@ >> Override pmtimer IOPort with a hex value. >> e.g. pmtmr=3D0x508 >>=20 >> + pmu=3D [PPC] Manually enable the PMU. >> + Enable the PMU by setting MMCR0 to 0 (clear FC bit). >> + This option is implemented for Book3S processors. >> + If a number is given, then MMCR1 is set to that number, >> + otherwise (e.g., 'pmu=3Don'), it is left 0. The perf >> + subsystem is disabled if this option is used. >> + >> pm_debug_messages [SUSPEND,KNL] >> Enable suspend/resume debug messages during boot up. >>=20 >> diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-bo= ok3s.c >> index 65795cadb475..e7cef4fe17d7 100644 >> --- a/arch/powerpc/perf/core-book3s.c >> +++ b/arch/powerpc/perf/core-book3s.c >> @@ -2428,8 +2428,24 @@ int register_power_pmu(struct power_pmu *pmu) >> } >>=20 >> #ifdef CONFIG_PPC64 >> +static bool pmu_override =3D false; >> +static unsigned long pmu_override_val; >> +static void do_pmu_override(void *data) >> +{ >> + ppc_set_pmu_inuse(1); >> + if (pmu_override_val) >> + mtspr(SPRN_MMCR1, pmu_override_val); >> + mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_FC); >=20 > Hi Nick >=20 > Here, we are not doing any validity check for the value used to set MMCR1= .=20 > For advanced users, the option to pass value for MMCR1 is fine. But other= cases, it could result in > invalid event getting used. Do we need to restrict this boot time option = for only PMC5/6 ? Depends what would be useful. We don't have to prevent the admin shooting=20 themselves in the foot with options like this, but if we can make it=20 safer without making it less useful then that's always a good option. Thanks, Nick