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[60.242.208.220]) by smtp.gmail.com with ESMTPSA id ca7sm337700pjb.11.2021.08.12.21.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 21:24:24 -0700 (PDT) Date: Fri, 13 Aug 2021 14:24:19 +1000 From: Nicholas Piggin Subject: Re: [PATCH v1 17/55] KVM: PPC: Book3S HV P9: Implement PMU save/restore in C To: Athira Rajeev References: <20210726035036.739609-1-npiggin@gmail.com> <20210726035036.739609-18-npiggin@gmail.com> <1A47BBEF-FC8C-4C4D-8393-9DE66B7FF96C@linux.vnet.ibm.com> In-Reply-To: <1A47BBEF-FC8C-4C4D-8393-9DE66B7FF96C@linux.vnet.ibm.com> MIME-Version: 1.0 Message-Id: <1628827731.ai2zz7xxwa.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, kvm-ppc@vger.kernel.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Athira Rajeev's message of August 9, 2021 1:03 pm: >=20 >=20 >> On 26-Jul-2021, at 9:19 AM, Nicholas Piggin wrote: >> +static void freeze_pmu(unsigned long mmcr0, unsigned long mmcra) >> +{ >> + if (!(mmcr0 & MMCR0_FC)) >> + goto do_freeze; >> + if (mmcra & MMCRA_SAMPLE_ENABLE) >> + goto do_freeze; >> + if (cpu_has_feature(CPU_FTR_ARCH_31)) { >> + if (!(mmcr0 & MMCR0_PMCCEXT)) >> + goto do_freeze; >> + if (!(mmcra & MMCRA_BHRB_DISABLE)) >> + goto do_freeze; >> + } >> + return; >> + >> +do_freeze: >> + mmcr0 =3D MMCR0_FC; >> + mmcra =3D 0; >> + if (cpu_has_feature(CPU_FTR_ARCH_31)) { >> + mmcr0 |=3D MMCR0_PMCCEXT; >> + mmcra =3D MMCRA_BHRB_DISABLE; >> + } >> + >> + mtspr(SPRN_MMCR0, mmcr0); >> + mtspr(SPRN_MMCRA, mmcra); >> + isync(); >> +} >> + > Hi Nick, >=20 > After feezing pmu, do we need to clear =E2=80=9Cpmcregs_in_use=E2=80=9D a= s well? Not until we save the values out of the registers. pmcregs_in_use =3D 0=20 means our hypervisor is free to clear our PMU register contents. > Also can=E2=80=99t we unconditionally do the MMCR0/MMCRA/ freeze settings= in here ? do we need the if conditions for FC/PMCCEXT/BHRB ? I think it's possible, but pretty minimal advantage. I would prefer to=20 set them the way perf does for now. If we can move this code into perf/ it should become easier for you to tweak things. Thanks, Nick