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[193.116.119.33]) by smtp.gmail.com with ESMTPSA id c16sm5945579pfb.196.2021.08.18.04.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Aug 2021 04:42:00 -0700 (PDT) Date: Wed, 18 Aug 2021 21:41:55 +1000 From: Nicholas Piggin Subject: Re: [PATCH v1 2/4] powerpc/64s/perf: add power_pmu_running to query whether perf is being used To: linuxppc-dev@lists.ozlabs.org, Madhavan Srinivasan References: <20210816072953.1165964-1-npiggin@gmail.com> <20210816072953.1165964-3-npiggin@gmail.com> <2e3108d7-8d11-d204-c605-fe51cd361586@linux.ibm.com> In-Reply-To: <2e3108d7-8d11-d204-c605-fe51cd361586@linux.ibm.com> MIME-Version: 1.0 Message-Id: <1629286381.q658eskbmg.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Athira Rajeev Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Madhavan Srinivasan's message of August 17, 2021 11:06 pm: >=20 > On 8/16/21 12:59 PM, Nicholas Piggin wrote: >> Interrupt handling code would like to know whether perf is enabled, to >> know whether it should enable MSR[EE] to improve PMI coverage. >> >> Cc: Madhavan Srinivasan >> Cc: Athira Rajeev >> Signed-off-by: Nicholas Piggin >> --- >> arch/powerpc/include/asm/hw_irq.h | 2 ++ >> arch/powerpc/perf/core-book3s.c | 13 +++++++++++++ >> 2 files changed, 15 insertions(+) >> >> diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/as= m/hw_irq.h >> index 21cc571ea9c2..2d5c0d3ccbb6 100644 >> --- a/arch/powerpc/include/asm/hw_irq.h >> +++ b/arch/powerpc/include/asm/hw_irq.h >> @@ -306,6 +306,8 @@ static inline bool lazy_irq_pending_nocheck(void) >> return __lazy_irq_pending(local_paca->irq_happened); >> } >> =20 >> +bool power_pmu_running(void); >> + >> /* >> * This is called by asynchronous interrupts to conditionally >> * re-enable hard interrupts after having cleared the source >> diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-bo= ok3s.c >> index bb0ee716de91..76114a9afb2b 100644 >> --- a/arch/powerpc/perf/core-book3s.c >> +++ b/arch/powerpc/perf/core-book3s.c >> @@ -2380,6 +2380,19 @@ static void perf_event_interrupt(struct pt_regs *= regs) >> perf_sample_event_took(sched_clock() - start_clock); >> } >> =20 >> +bool power_pmu_running(void) >> +{ >> + struct cpu_hw_events *cpuhw; >> + >> + /* Could this simply test local_paca->pmcregs_in_use? */ >> + >> + if (!ppmu) >> + return false; >=20 >=20 > This covers only when perf platform driver is not registered, > but we should also check for MMCR0[32], since pmu sprs can be > accessed via sysfs. In that case do they actually do anything with the PMI? I don't think it=20 should matter hopefully. But I do think a lot of this stuff could be cleaned up. We have=20 pmcs_enabled and ppc_enable_pmcs() in sysfs.c, ppc_set_pmu_inuse(),=20 ppc_md.enable_pmcs(), reserve_pmc_hardware(), etc and different users=20 call different things. We don't consistently disable either, e.g., we=20 never disable the H_PERFMON facility after we stop using perf even=20 though it says that slows down partition switch. I started to have a look at sorting it out but it looks like a big job so would take a bit of time if we want to do it. Thanks, Nick