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[193.116.119.33]) by smtp.gmail.com with ESMTPSA id l14sm6684825pjq.13.2021.08.25.20.26.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Aug 2021 20:26:19 -0700 (PDT) Date: Thu, 26 Aug 2021 13:26:14 +1000 From: Nicholas Piggin Subject: Re: [PATCH v2 1/2] powerpc/bug: Remove specific powerpc BUG_ON() and WARN_ON() on PPC32 To: Segher Boessenkool References: <1628834356.pr4zgn1xf1.astroid@bobo.none> <20210818150653.GJ1583@gate.crashing.org> In-Reply-To: <20210818150653.GJ1583@gate.crashing.org> MIME-Version: 1.0 Message-Id: <1629946707.f6ptz0tgle.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, Paul Mackerras , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Segher Boessenkool's message of August 19, 2021 1:06 am: > On Fri, Aug 13, 2021 at 04:08:13PM +1000, Nicholas Piggin wrote: >> This one possibly the branches end up in predictors, whereas conditional= =20 >> trap is always just speculated not to hit. Branches may also have a >> throughput limit on execution whereas trap could be more (1 per cycle >> vs 4 per cycle on POWER9). >=20 > I thought only *taken* branches are just one per cycle? Taken branches are fetched by the front end at one per cycle (assuming=20 they hit the BTAC), but all branches have to be executed by BR at one=20 per cycle. On POWER9 BR even has to execute some other things like mflr as well, but at least that's improved on POWER10. Trap is executed at 4 per cycle and will never use branch table entries=20 or alias with a non-tagged predictor and mispredict. > And those > branches are only taken for the exceptional condition (or the case where > we do not care about performance, anyway, if we do have an error most of > the time ;-) ) It's not that big a deal, but trap is really the best instruction for=20 this. >=20 >> On typical ppc32 CPUs, maybe it's a more obvious win. As you say there >> is the CFAR issue as well which makes it a problem for 64s. It would >> have been nice if it could use the same code though. >=20 > On 64-bit the code looks better for the no-error path as well. >=20 >> Maybe one day gcc's __builtin_trap() will become smart enough around >> conditional statements that it it generates better code and tries to >> avoid branches. >=20 > Internally *all* traps are conditional, in GCC. It also can optimise > them quite well. There must be something in the kernel macros that > prevents good optimisation. I did take a look at it at one point. One problem is that the kernel needs the address of the trap instruction=20 to create the entry for it. The other problem is that __builtin_trap=20 does not return so it can't be used for WARN. LLVM at least seems to=20 have a __builtin_debugtrap which does return. The first problem seems like the show stopper though. AFAIKS it would=20 need a special builtin support that does something to create the table entry, or a guarantee that we could put an inline asm right after the builtin as a recognized pattern and that would give us the instruction following the trap. Thanks, Nick