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[220.244.72.10]) by smtp.gmail.com with ESMTPSA id t12sm4063689pgo.56.2021.08.26.06.57.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 06:57:58 -0700 (PDT) Date: Thu, 26 Aug 2021 23:57:52 +1000 From: Nicholas Piggin Subject: Re: [PATCH v2 1/2] powerpc/bug: Remove specific powerpc BUG_ON() and WARN_ON() on PPC32 To: Segher Boessenkool References: <1628834356.pr4zgn1xf1.astroid@bobo.none> <20210818150653.GJ1583@gate.crashing.org> <1629946707.f6ptz0tgle.astroid@bobo.none> <20210826124901.GY1583@gate.crashing.org> In-Reply-To: <20210826124901.GY1583@gate.crashing.org> MIME-Version: 1.0 Message-Id: <1629983260.5jkx2jf0y8.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, Paul Mackerras , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Segher Boessenkool's message of August 26, 2021 10:49 pm: > Hi! >=20 > On Thu, Aug 26, 2021 at 01:26:14PM +1000, Nicholas Piggin wrote: >> Excerpts from Segher Boessenkool's message of August 19, 2021 1:06 am: >> > On Fri, Aug 13, 2021 at 04:08:13PM +1000, Nicholas Piggin wrote: >> >> This one possibly the branches end up in predictors, whereas conditio= nal=20 >> >> trap is always just speculated not to hit. Branches may also have a >> >> throughput limit on execution whereas trap could be more (1 per cycle >> >> vs 4 per cycle on POWER9). >> >=20 >> > I thought only *taken* branches are just one per cycle? >>=20 >> Taken branches are fetched by the front end at one per cycle (assuming=20 >> they hit the BTAC), but all branches have to be executed by BR at one=20 >> per cycle >=20 > This is not true. (Simple) predicted not-taken conditional branches are > just folded out, never hit the issue queues. And they are fetched as > many together as fit in a fetch group, can complete without limits as > well. No, they are all dispatched and issue to the BRU for execution. It's=20 trivial to construct a test of a lot of not taken branches in a row and time a loop of it to see it executes at 1 cycle per branch. > The BTAC is a frontend thing, used for target address prediction. It > does not limit execution. I didn't say it did. > Correctly predicted simple conditional branches just get their prediction > validated (and that is not done in the execution units). Incorrectly > predicted branches the same, but those cause a redirect and refetch. How could it validate prediction without issuing? It wouldn't know when sources are ready. >=20 >> > Internally *all* traps are conditional, in GCC. It also can optimise >> > them quite well. There must be something in the kernel macros that >> > prevents good optimisation. >>=20 >> I did take a look at it at one point. >>=20 >> One problem is that the kernel needs the address of the trap instruction= =20 >> to create the entry for it. The other problem is that __builtin_trap=20 >> does not return so it can't be used for WARN. LLVM at least seems to=20 >> have a __builtin_debugtrap which does return. >=20 > This is . Aha. >> The first problem seems like the show stopper though. AFAIKS it would=20 >> need a special builtin support that does something to create the table >> entry, or a guarantee that we could put an inline asm right after the >> builtin as a recognized pattern and that would give us the instruction >> following the trap. >=20 > I'm not quite sure what this means. Can't you always just put a >=20 > bla: asm(""); >=20 > in there, and use the address of "bla"? Not AFAIKS. Put it where? > If not, you need to say a lot > more about what you actually want to do :-/ We need to put the address (or relative offset) of the trap instruction into an entry in a different section. Basically this: __builtin_trap(); asm ("1: \n\t" " .section __bug_table,\"aw\" \n\t" "2: .4byte 1b - 2b - 4 \n\t" " .previous"); Where the 1: label must follow immediately after the trap instruction,=20 and where the asm must be emitted even for the case of no-return traps=20 (but anything following the asm could be omitted). Thanks, Nick