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Wed, 27 Oct 2021 20:01:33 -0700 (PDT) Received: from localhost ([118.208.159.180]) by smtp.gmail.com with ESMTPSA id x5sm1322015pfh.153.2021.10.27.20.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Oct 2021 20:01:33 -0700 (PDT) Date: Thu, 28 Oct 2021 13:01:27 +1000 From: Nicholas Piggin Subject: Re: instruction storage exception handling To: Christophe Leroy , Jacques de Laval References: <1635306738.0z8wt7619v.astroid@bobo.none> <1f5c24de-6bba-d6c0-5b8e-3522f25158f6@csgroup.eu> <1635312278.p87nvl11rv.astroid@bobo.none> <4ee635f5-7a67-bac5-2ad2-616c1aaa95b6@csgroup.eu> <1635318932.od1ierwsis.astroid@bobo.none> In-Reply-To: MIME-Version: 1.0 Message-Id: <1635389034.knz9p2g41k.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Scott Wood , "linuxppc-dev@lists.ozlabs.org" Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Jacques de Laval's message of October 27, 2021 10:03 pm: > On Wednesday, October 27th, 2021 at 9:52 AM, Christophe Leroy wrote: >=20 >> Le 27/10/2021 =C3=A0 09:47, Nicholas Piggin a =C3=A9crit=C2=A0: >> >> > You're right. In that case it shouldn't change anything unless there >> > >> > was a BO fault. I'm not sure what the problem is then. Guessing based >> > >> > on the NIP and instructions, it looks like it's probably got the corre= ct >> > >> > user address that it's storing into vmf on the stack, so it has got pa= st >> > >> > the access checks so my theory would be wrong anyway. >> > >> > Must be something simple but I can't see it yet. >> >> Anyway, I think it is still worth doing the check with setting 0 in >> >> _ESR(r11), maybe the Reference Manual is wrong. >> >> So Jacques, please do the test anyway if you can. >> >> Thanks >> >> Christophe >=20 > I tested with the last patch from Nicholas, and with that I can not > reproduce the issue, so it seems like that solves it for my case and setu= p > at least. >=20 > Big thanks Christophe and Nicholas for looking in to this! Thanks for reporting and testing. We can certainly send this patch=20 upstream to fix the regression, but I'm still not exactly sure what is=20 going on. If it is an errata or part of specification we missed that=20 could explain it but it would be good to understand and comment it. If you have time to test again with only the following patch applied, it might give a better clue. This patch should keep running but it would print some dmesg output. Thanks, Nick diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c index a8d0ce85d39a..cf56f23ff90a 100644 --- a/arch/powerpc/mm/fault.c +++ b/arch/powerpc/mm/fault.c @@ -548,6 +548,12 @@ static __always_inline void __do_page_fault(struct pt_= regs *regs) =20 DEFINE_INTERRUPT_HANDLER(do_page_fault) { + if (TRAP(regs) =3D=3D INTERRUPT_INST_STORAGE) { + if (regs->dsisr !=3D 0) { + printk("ISI pc:%lx msr:%lx dsisr:%lx ESR:%lx\n", regs->nip, regs->msr, = regs->dsisr, mfspr(SPRN_ESR)); + regs->dsisr =3D 0; // fix? + } + } __do_page_fault(regs); } =20