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* [PATCH] ASoC: fsl_xcvr: Enable 2 * TX bit clock for spdif only case
@ 2023-11-22  1:42 Shengjiu Wang
  2023-11-22 17:31 ` Mark Brown
  0 siblings, 1 reply; 2+ messages in thread
From: Shengjiu Wang @ 2023-11-22  1:42 UTC (permalink / raw)
  To: nicoleotsuka, Xiubo.Lee, festevam, shengjiu.wang, lgirdwood,
	broonie, perex, tiwai, alsa-devel
  Cc: linuxppc-dev, linux-kernel

The bit 10 in TX_DPTH_CTRL register controls the TX clock rate.
If this bit is set, TX datapath clock should be = 2* TX bit rate.
If this bit is not set, TX datapath clock should be 10* TX bit rate.

As the spdif only case, we always use 2 * TX bit clock, so
this bit need to be set.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
 sound/soc/fsl/fsl_xcvr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
index fa0a15263c66..77f8e2394bf9 100644
--- a/sound/soc/fsl/fsl_xcvr.c
+++ b/sound/soc/fsl/fsl_xcvr.c
@@ -414,6 +414,16 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream,
 
 	switch (xcvr->mode) {
 	case FSL_XCVR_MODE_SPDIF:
+		if (xcvr->soc_data->spdif_only && tx) {
+			ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET,
+						 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM,
+						 FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM);
+			if (ret < 0) {
+				dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret);
+				return ret;
+			}
+		}
+		fallthrough;
 	case FSL_XCVR_MODE_ARC:
 		if (tx) {
 			ret = fsl_xcvr_en_aud_pll(xcvr, fout);
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] ASoC: fsl_xcvr: Enable 2 * TX bit clock for spdif only case
  2023-11-22  1:42 [PATCH] ASoC: fsl_xcvr: Enable 2 * TX bit clock for spdif only case Shengjiu Wang
@ 2023-11-22 17:31 ` Mark Brown
  0 siblings, 0 replies; 2+ messages in thread
From: Mark Brown @ 2023-11-22 17:31 UTC (permalink / raw)
  To: nicoleotsuka, Xiubo.Lee, festevam, shengjiu.wang, lgirdwood,
	perex, tiwai, alsa-devel, Shengjiu Wang
  Cc: linuxppc-dev, linux-kernel

On Wed, 22 Nov 2023 09:42:53 +0800, Shengjiu Wang wrote:
> The bit 10 in TX_DPTH_CTRL register controls the TX clock rate.
> If this bit is set, TX datapath clock should be = 2* TX bit rate.
> If this bit is not set, TX datapath clock should be 10* TX bit rate.
> 
> As the spdif only case, we always use 2 * TX bit clock, so
> this bit need to be set.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/1] ASoC: fsl_xcvr: Enable 2 * TX bit clock for spdif only case
      commit: c33fd110424dfcb544cf55a1b312f43fe1918235

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark


^ permalink raw reply	[flat|nested] 2+ messages in thread

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