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From: Alistair Popple <alistair@popple.id.au>
To: linuxppc-dev@lists.ozlabs.org
Cc: Nicholas Piggin <nicholas.piggin@gmail.com>,
	Frederic Barrat <fbarrat@linux.vnet.ibm.com>,
	clombard@linux.vnet.ibm.com, vaibhav@linux.vnet.ibm.com,
	andrew.donnellan@au1.ibm.com
Subject: Re: [PATCH v3 2/2] cxl: Enable global TLBIs for cxl contexts
Date: Wed, 13 Sep 2017 13:53:22 +1000	[thread overview]
Message-ID: <1722769.VMcgIllh4T@new-mexico> (raw)
In-Reply-To: <20170908165624.22dca915@roar.ozlabs.ibm.com>

On Fri, 8 Sep 2017 04:56:24 PM Nicholas Piggin wrote:
> On Sun,  3 Sep 2017 20:15:13 +0200
> Frederic Barrat <fbarrat@linux.vnet.ibm.com> wrote:
> 
> > The PSL and nMMU need to see all TLB invalidations for the memory
> > contexts used on the adapter. For the hash memory model, it is done by
> > making all TLBIs global as soon as the cxl driver is in use. For
> > radix, we need something similar, but we can refine and only convert
> > to global the invalidations for contexts actually used by the device.
> > 
> > The new mm_context_add_copro() API increments the 'active_cpus' count
> > for the contexts attached to the cxl adapter. As soon as there's more
> > than 1 active cpu, the TLBIs for the context become global. Active cpu
> > count must be decremented when detaching to restore locality if
> > possible and to avoid overflowing the counter.
> > 
> > The hash memory model support is somewhat limited, as we can't
> > decrement the active cpus count when mm_context_remove_copro() is
> > called, because we can't flush the TLB for a mm on hash. So TLBIs
> > remain global on hash.
> 
> Sorry I didn't look at this earlier and just wading in here a bit, but
> what do you think of using mmu notifiers for invalidating nMMU and
> coprocessor caches, rather than put the details into the host MMU
> management? npu-dma.c already looks to have almost everything covered
> with its notifiers (in that it wouldn't have to rely on tlbie coming
> from host MMU code).

Sorry, just finding time to catch up on this. From subsequent emails it looks
like you may have figured this out. The TLB flush in npu-dma.c is a workaround
for a HW issue rather than there to explicitly manage the NMMU caches. The
intent for NPU was always to have the NMMU snoop normal core tlbies rather than
do it via notifiers. A subsequent patch series
(https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=1681) removes
this flush now that the HW issue has been worked around via a FW fix.

I agree this is something we could look into optimising in the medium term, but
for the moment it would be good if we could get this series merged.

- Alistair

  parent reply	other threads:[~2017-09-13  3:53 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-03 18:15 [PATCH v3 1/2] powerpc/mm: Export flush_all_mm() Frederic Barrat
2017-09-03 18:15 ` [PATCH v3 2/2] cxl: Enable global TLBIs for cxl contexts Frederic Barrat
2017-09-08  6:56   ` Nicholas Piggin
2017-09-08  7:34     ` Frederic Barrat
2017-09-08 10:54       ` Nicholas Piggin
2017-09-08 11:18         ` Nicholas Piggin
2017-09-13  3:53     ` Alistair Popple [this message]
2017-09-13  3:58   ` Alistair Popple
2017-09-13  4:04 ` [PATCH v3 1/2] powerpc/mm: Export flush_all_mm() Alistair Popple
2017-09-13  8:34   ` Frederic Barrat
2017-10-05  4:21 ` [v3,1/2] " Michael Ellerman

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