From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Message-ID: <17348.50913.414568.263736@cargo.ozlabs.ibm.com> Date: Wed, 11 Jan 2006 19:50:41 +1100 From: Paul Mackerras To: Eugene Surovegin In-Reply-To: <20060111071032.GA28843@gate.ebshome.net> References: <17348.35120.840409.283964@cargo.ozlabs.ibm.com> <17348.37558.434652.697604@cargo.ozlabs.ibm.com> <20060111071032.GA28843@gate.ebshome.net> Cc: linuxppc64-dev@ozlabs.org, Kumar Gala , sjmunroe@us.ibm.com, linuxppc-dev@ozlabs.org Subject: Re: [PATCH] implement AT_PLATFORM for powerpc List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Eugene Surovegin writes: > I checked 44x user manuals I have: > > 440GP doesn't have isel > 440GX, 440EP, 440SP, 440SPe, 440GR have it. Thanks, that's helpful. Do you know if 440{GX,EP,SP,SPe,GR} implement all of the 32-bit user-mode instructions in Book E? How do mbar and msync work on those processors? As mbar and msync (as defined in Book E) or as eieio and sync? Do the 440* processors in fact claim Book E compliance? Thanks, Paul.