From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Message-ID: <17633.18057.778991.483461@cargo.ozlabs.ibm.com> Date: Tue, 15 Aug 2006 13:59:05 +1000 From: Paul Mackerras To: Subject: RE: PowerPC paxtest results w/ gcc-4.1 In-Reply-To: <000301c6bf97$e9151e00$99dfdfdf@bakuhatsu.net> References: <17630.27174.711916.643790@cargo.ozlabs.ibm.com> <000301c6bf97$e9151e00$99dfdfdf@bakuhatsu.net> Cc: 'Albert Cahalan' , linuxppc-dev@ozlabs.org, debian-powerpc@lists.debian.org List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Matt Sealey writes: > Book I compatible PowerPC's have had a "no-executable" bit in > the page protection flags since the dark ages.. see page 7-38 > and 7-39 of the 'Programming Environments Manual for 32-Bit > Microprocessors'.. this document predates even the G3. What are you referring to? I have a copy of the PEM from pre-G3 days, and a copy that I downloaded just now, and neither of them have an N bit in the PTE (and yes I just looked carefully through pages 7-38 and 7-39). There is an N bit in the segment register format, and that's what Albert is using. > As far as the documentation goes, you can make the page > readable and writable to the LSU, but the N bit causes the > instruction fetch to cause a machine check. That's pretty > "not-executable" to me at least :) A machine check is nasty, because it may not be recoverable... Paul.