From: "Christophe Leroy (CS GROUP)" <chleroy@kernel.org>
To: Qiang Zhao <qiang.zhao@nxp.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
"Christophe Leroy (CS GROUP)" <chleroy@kernel.org>
Cc: linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports
Date: Wed, 28 Jan 2026 12:04:04 +0100 [thread overview]
Message-ID: <176959816683.2069840.8945134159377635375.b4-ty@kernel.org> (raw)
In-Reply-To: <63f19db21a91729d91b3df336a56a7eb4206e561.1767804922.git.chleroy@kernel.org>
On Wed, 07 Jan 2026 17:59:09 +0100, Christophe Leroy (CS GROUP) wrote:
> The QUICC Engine provides interrupts for a few I/O ports. This is
> handled via a separate interrupt ID and managed via a triplet of
> dedicated registers hosted by the SoC.
>
> Implement an interrupt driver for it so that those IRQs can then
> be linked to the related GPIOs.
>
> [...]
Applied, thanks!
[1/2] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports
[2/2] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports
Best regards,
--
Christophe Leroy (CS GROUP) <chleroy@kernel.org>
prev parent reply other threads:[~2026-01-28 11:04 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-07 16:59 [PATCH 1/2] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Christophe Leroy (CS GROUP)
2026-01-07 16:59 ` [PATCH 2/2] dt-bindings: " Christophe Leroy (CS GROUP)
2026-01-08 19:02 ` Rob Herring
2026-01-08 19:44 ` Christophe Leroy (CS GROUP)
2026-01-08 20:09 ` Rob Herring
2026-01-28 11:04 ` Christophe Leroy (CS GROUP) [this message]
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