[PATCH 2/2] [PPC 44x] enable L2-cache for ALPR, Katmai, Ocotea, and Taishan

[PATCH 2/2] [PPC 44x] enable L2-cache for ALPR, Katmai, Ocotea, and Taishan

[Yuri Tikhonov]

 This patch introduces the L2_CACHE configuration option available
for the ppc44x-based boards with L2-cache enabled.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Pavel Kolesnikov <concord@emcraft.com>

--
diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index 1d2ca42..ad6b581 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -396,4 +396,12 @@ config SERIAL_SICC_CONSOLE
        bool
        depends on SERIAL_SICC && UART0_TTYS1
        default y
+
+config L2_CACHE
+       bool "Enable Level-2 Cache"
+       depends on NOT_COHERENT_CACHE && (KATMAI || TAISHAN || OCOTEA || ALPR)
+       default y
+       help
+         This option enables L2-cache on ppc44x controllers.
+         If unsure, say Y.
 endmenu
diff --git a/arch/ppc/platforms/4xx/alpr.c b/arch/ppc/platforms/4xx/alpr.c
index 3b6519f..0623801 100644
--- a/arch/ppc/platforms/4xx/alpr.c
+++ b/arch/ppc/platforms/4xx/alpr.c
@@ -537,10 +537,12 @@ static void __init alpr_setup_arch(void)
        printk("Prodrive ALPR port (DENX Software Engineering <sr@denx.de>)\n");
 }
 
+#ifdef CONFIG_L2_CACHE
 static void __init alpr_init(void)
 {
        ibm440gx_l2c_setup(&clocks);
 }
+#endif
 
 static void alpr_progress(char *buf, unsigned short val)
 {
@@ -567,7 +569,9 @@ void __init platform_init(unsigned long r3, unsigned long r4,
 #ifdef CONFIG_KGDB
        ppc_md.early_serial_map = alpr_early_serial_map;
 #endif
+#ifdef CONFIG_L2_CACHE
        ppc_md.init = alpr_init;
+#endif
        ppc_md.restart = alpr_restart;
 }
 
diff --git a/arch/ppc/platforms/4xx/katmai.c b/arch/ppc/platforms/4xx/katmai.c
index d29ebf6..01f1baf 100644
--- a/arch/ppc/platforms/4xx/katmai.c
+++ b/arch/ppc/platforms/4xx/katmai.c
@@ -219,6 +219,7 @@ katmai_show_cpuinfo(struct seq_file *m)
 {
        seq_printf(m, "vendor\t\t: AMCC\n");
        seq_printf(m, "machine\t\t: PPC440SPe EVB (Katmai)\n");
+       ibm440gx_show_cpuinfo(m);
 
        return 0;
 }
@@ -584,6 +585,13 @@ static void katmai_restart(char *cmd)
        mtspr(SPRN_DBCR0, DBCR0_RST_CHIP);
 }
 
+#ifdef CONFIG_L2_CACHE
+static void __init katmai_init(void)
+{
+       ibm440gx_l2c_setup(&clocks);
+}
+#endif
+
 void __init platform_init(unsigned long r3, unsigned long r4,
                          unsigned long r5, unsigned long r6, unsigned long r7)
 {
@@ -599,4 +607,7 @@ void __init platform_init(unsigned long r3, unsigned long r4,
        ppc_md.early_serial_map = katmai_early_serial_map;
 #endif
        ppc_md.restart = katmai_restart;
+#ifdef CONFIG_L2_CACHE
+       ppc_md.init = katmai_init;
+#endif
 }
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
index a7435aa..8b13811 100644
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ b/arch/ppc/platforms/4xx/ocotea.c
@@ -321,10 +321,12 @@ ocotea_setup_arch(void)
        printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
 }
 
+#ifdef CONFIG_L2_CACHE
 static void __init ocotea_init(void)
 {
        ibm440gx_l2c_setup(&clocks);
 }
+#endif
 
 void __init platform_init(unsigned long r3, unsigned long r4,
                unsigned long r5, unsigned long r6, unsigned long r7)
@@ -345,5 +347,7 @@ void __init platform_init(unsigned long r3, unsigned long r4,
 #ifdef CONFIG_KGDB
        ppc_md.early_serial_map = ocotea_early_serial_map;
 #endif
+#ifdef CONFIG_L2_CACHE
        ppc_md.init = ocotea_init;
+#endif
 }
diff --git a/arch/ppc/platforms/4xx/taishan.c b/arch/ppc/platforms/4xx/taishan.c
index f4b9435..8bb6f15 100644
--- a/arch/ppc/platforms/4xx/taishan.c
+++ b/arch/ppc/platforms/4xx/taishan.c
@@ -370,10 +370,12 @@ taishan_setup_arch(void)
        printk("AMCC PowerPC 440GX Taishan Platform\n");
 }
 
+#ifdef CONFIG_L2_CACHE
 static void __init taishan_init(void)
 {
        ibm440gx_l2c_setup(&clocks);
 }
+#endif
 
 void __init platform_init(unsigned long r3, unsigned long r4,
                unsigned long r5, unsigned long r6, unsigned long r7)
@@ -389,6 +391,8 @@ void __init platform_init(unsigned long r3, unsigned long r4,
 #ifdef CONFIG_KGDB
        ppc_md.early_serial_map = taishan_early_serial_map;
 #endif
+#ifdef CONFIG_L2_CACHE
        ppc_md.init = taishan_init;
+#endif
 }
   

Re: [PATCH 2/2] [PPC 44x] enable L2-cache for ALPR, Katmai, Ocotea, and Taishan

[Olof Johansson]

Hi,

See comments below.


-Olof

On Wed, Nov 07, 2007 at 01:40:41AM +0300, Yuri Tikhonov wrote:
>  This patch introduces the L2_CACHE configuration option available
> for the ppc44x-based boards with L2-cache enabled.
> 
> Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
> Signed-off-by: Pavel Kolesnikov <concord@emcraft.com>
> 
> --
> diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
> index 1d2ca42..ad6b581 100644
> --- a/arch/ppc/platforms/4xx/Kconfig
> +++ b/arch/ppc/platforms/4xx/Kconfig
> @@ -396,4 +396,12 @@ config SERIAL_SICC_CONSOLE
>         bool
>         depends on SERIAL_SICC && UART0_TTYS1
>         default y
> +
> +config L2_CACHE
> +       bool "Enable Level-2 Cache"
> +       depends on NOT_COHERENT_CACHE && (KATMAI || TAISHAN || OCOTEA || ALPR)
> +       default y
> +       help
> +         This option enables L2-cache on ppc44x controllers.
> +         If unsure, say Y.

That's a very generic config name. Maybe something like PPC_4XX_L2_CACHE?

Is there ever a case where a user would NOT want l2 cache enabled (and
disabled permanently enough to rebuild the kernel instead of giving a
kernel command line option?)

>  endmenu
> diff --git a/arch/ppc/platforms/4xx/alpr.c b/arch/ppc/platforms/4xx/alpr.c
> index 3b6519f..0623801 100644
> --- a/arch/ppc/platforms/4xx/alpr.c
> +++ b/arch/ppc/platforms/4xx/alpr.c
> @@ -537,10 +537,12 @@ static void __init alpr_setup_arch(void)
>         printk("Prodrive ALPR port (DENX Software Engineering <sr@denx.de>)\n");
>  }
>  
> +#ifdef CONFIG_L2_CACHE
>  static void __init alpr_init(void)
>  {
>         ibm440gx_l2c_setup(&clocks);
>  }
> +#endif
>  
>  static void alpr_progress(char *buf, unsigned short val)
>  {
> @@ -567,7 +569,9 @@ void __init platform_init(unsigned long r3, unsigned long r4,
>  #ifdef CONFIG_KGDB
>         ppc_md.early_serial_map = alpr_early_serial_map;
>  #endif
> +#ifdef CONFIG_L2_CACHE
>         ppc_md.init = alpr_init;
> +#endif

Why do you take out the above calls if the new option is selected? Seems
odd to remove something that worked(?) before.

>         ppc_md.restart = alpr_restart;
>  }
>  
> diff --git a/arch/ppc/platforms/4xx/katmai.c b/arch/ppc/platforms/4xx/katmai.c
> index d29ebf6..01f1baf 100644
> --- a/arch/ppc/platforms/4xx/katmai.c
> +++ b/arch/ppc/platforms/4xx/katmai.c
> @@ -219,6 +219,7 @@ katmai_show_cpuinfo(struct seq_file *m)
>  {
>         seq_printf(m, "vendor\t\t: AMCC\n");
>         seq_printf(m, "machine\t\t: PPC440SPe EVB (Katmai)\n");
> +       ibm440gx_show_cpuinfo(m);

This seems unrelated to this patch.

>         return 0;
>  }
> @@ -584,6 +585,13 @@ static void katmai_restart(char *cmd)
>         mtspr(SPRN_DBCR0, DBCR0_RST_CHIP);
>  }
>  
> +#ifdef CONFIG_L2_CACHE
> +static void __init katmai_init(void)
> +{
> +       ibm440gx_l2c_setup(&clocks);
> +}
> +#endif
> +
>  void __init platform_init(unsigned long r3, unsigned long r4,
>                           unsigned long r5, unsigned long r6, unsigned long r7)
>  {
> @@ -599,4 +607,7 @@ void __init platform_init(unsigned long r3, unsigned long r4,
>         ppc_md.early_serial_map = katmai_early_serial_map;
>  #endif
>         ppc_md.restart = katmai_restart;
> +#ifdef CONFIG_L2_CACHE
> +       ppc_md.init = katmai_init;
> +#endif

See comment above. Should the above init be called for all configs, not just
when L2_CACHE is enabled?

Also, it looks like the init function is the same on every board. It would
be better to make a common function instead of duplicating it everywhere.

>  }
> diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
> index a7435aa..8b13811 100644
> --- a/arch/ppc/platforms/4xx/ocotea.c
> +++ b/arch/ppc/platforms/4xx/ocotea.c
> @@ -321,10 +321,12 @@ ocotea_setup_arch(void)
>         printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
>  }
>  
> +#ifdef CONFIG_L2_CACHE
>  static void __init ocotea_init(void)
>  {
>         ibm440gx_l2c_setup(&clocks);
>  }
> +#endif
>  
>  void __init platform_init(unsigned long r3, unsigned long r4,
>                 unsigned long r5, unsigned long r6, unsigned long r7)
> @@ -345,5 +347,7 @@ void __init platform_init(unsigned long r3, unsigned long r4,
>  #ifdef CONFIG_KGDB
>         ppc_md.early_serial_map = ocotea_early_serial_map;
>  #endif
> +#ifdef CONFIG_L2_CACHE
>         ppc_md.init = ocotea_init;
> +#endif
>  }
> diff --git a/arch/ppc/platforms/4xx/taishan.c b/arch/ppc/platforms/4xx/taishan.c
> index f4b9435..8bb6f15 100644
> --- a/arch/ppc/platforms/4xx/taishan.c
> +++ b/arch/ppc/platforms/4xx/taishan.c
> @@ -370,10 +370,12 @@ taishan_setup_arch(void)
>         printk("AMCC PowerPC 440GX Taishan Platform\n");
>  }
>  
> +#ifdef CONFIG_L2_CACHE
>  static void __init taishan_init(void)
>  {
>         ibm440gx_l2c_setup(&clocks);
>  }
> +#endif
>  
>  void __init platform_init(unsigned long r3, unsigned long r4,
>                 unsigned long r5, unsigned long r6, unsigned long r7)
> @@ -389,6 +391,8 @@ void __init platform_init(unsigned long r3, unsigned long r4,
>  #ifdef CONFIG_KGDB
>         ppc_md.early_serial_map = taishan_early_serial_map;
>  #endif
> +#ifdef CONFIG_L2_CACHE
>         ppc_md.init = taishan_init;
> +#endif
>  }
>    
> 
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev

Re[2]: [PATCH 2/2] [PPC 44x] enable L2-cache for ALPR, Katmai, Ocotea, and Taishan

[Yuri Tikhonov]

 Hi Olof,

On 07.11.2007, 7:06:08 you wrote:
...
>> +
>> +config L2_CACHE
>> +       bool "Enable Level-2 Cache"
>> +       depends on NOT_COHERENT_CACHE && (KATMAI || TAISHAN || OCOTEA || ALPR)
>> +       default y
>> +       help
>> +         This option enables L2-cache on ppc44x controllers.
>> +         If unsure, say Y.

> That's a very generic config name. Maybe something like PPC_4XX_L2_CACHE?

 Having the ppc_machdep for invalidating L2-cache lines we can avoid introducing the new configuration options at all. See below.

> Is there ever a case where a user would NOT want l2 cache enabled (and
> disabled permanently enough to rebuild the kernel instead of giving a
> kernel command line option?)

 Theoretically - yes. Internal SRAM of ppc44x may be used for something else than L2 cache. 

 Admittedly, the configuration option was necessary for me to enable or disable my L2-cache synchronization routine in the generic dma_sync() function. Per your suggestion, now, instead of introducing the new kernel option I initialize the L2-cache sync ppc_machdep right in the L2-cache enable routine: thus if the user will not enable L2-cache (will not want internal SRAM to act as L2-cache and will not call the L2-cache enabling routine) then my new ppc_machdep will remain set to zero and will not affect on SRAM used for some specific purposes.

...

>> @@ -567,7 +569,9 @@ void __init platform_init(unsigned long r3, unsigned long r4,
>>  #ifdef CONFIG_KGDB
>>         ppc_md.early_serial_map = alpr_early_serial_map;
>>  #endif
>> +#ifdef CONFIG_L2_CACHE
>>         ppc_md.init = alpr_init;
>> +#endif

> Why do you take out the above calls if the new option is selected? Seems
> odd to remove something that worked(?) before.

 Umm.. Quite the contrary, the option selected made these calls avaiable. Though it doesn't matter anymore since there is no CONFIG_L2_CACHE option anymore (i.e. all the four boards dealt with in this patch-set now have L2-cache enabled regardless of configuration, as it was initially).

>>         ppc_md.restart = alpr_restart;
>>  }
>>  

...

>> +#ifdef CONFIG_L2_CACHE
>> +static void __init katmai_init(void)
>> +{
>> +       ibm440gx_l2c_setup(&clocks);
>> +}
>> +#endif
>> +
>>  void __init platform_init(unsigned long r3, unsigned long r4,
>>                           unsigned long r5, unsigned long r6, unsigned long r7)
>>  {
>> @@ -599,4 +607,7 @@ void __init platform_init(unsigned long r3, unsigned long r4,
>>         ppc_md.early_serial_map = katmai_early_serial_map;
>>  #endif
>>         ppc_md.restart = katmai_restart;
>> +#ifdef CONFIG_L2_CACHE
>> +       ppc_md.init = katmai_init;
>> +#endif

> See comment above. Should the above init be called for all configs, not just
> when L2_CACHE is enabled?

> Also, it looks like the init function is the same on every board. It would
> be better to make a common function instead of duplicating it everywhere.

 Agree, but perhaps it's not the case for the ppc branch. Will do this in the powerpc branch as soon as support for these boards will be ported there.. by someone :)

Regards,
 Yuri 

-- 
Yuri Tikhonov, Senior Software Engineer
Emcraft Systems, www.emcraft.com

Re: [PATCH 2/2] [PPC 44x] enable L2-cache for ALPR, Katmai, Ocotea, and Taishan

[Benjamin Herrenschmidt]

BTW... Do you know why we can't just enable HW snoop ? The 440SPe
documentation seems to indicate that this is supported by the L2 cache
via snooping on the PLB.

Cheers,
Ben.

Re: [PATCH 2/2] [PPC 44x] enable L2-cache for ALPR, Katmai, Ocotea, and Taishan

[Eugene Surovegin]

On Tue, Nov 27, 2007 at 10:41:46AM +1100, Benjamin Herrenschmidt wrote:
> BTW... Do you know why we can't just enable HW snoop ? The 440SPe
> documentation seems to indicate that this is supported by the L2 cache
> via snooping on the PLB.

Unless something has been changed significantly in the 44x port, but 
L2 cache code I wrote for 440GX did exactly this - we never needed any 
manual L2 cache management at all.

-- 
Eugene

Re: [PATCH 2/2] [PPC 44x] enable L2-cache for ALPR, Katmai, Ocotea, and Taishan

[Benjamin Herrenschmidt]

On Wed, 2007-11-28 at 11:47 -0800, Eugene Surovegin wrote:
> On Tue, Nov 27, 2007 at 10:41:46AM +1100, Benjamin Herrenschmidt wrote:
> > BTW... Do you know why we can't just enable HW snoop ? The 440SPe
> > documentation seems to indicate that this is supported by the L2 cache
> > via snooping on the PLB.
> 
> Unless something has been changed significantly in the 44x port, but 
> L2 cache code I wrote for 440GX did exactly this - we never needed any 
> manual L2 cache management at all.

Ah good. So we should port that code over instead.

Thanks !
Ben.