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Mon, 20 Jul 2020 09:39:56 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5B36511C054; Mon, 20 Jul 2020 09:39:56 +0000 (GMT) Received: from pomme.local (unknown [9.145.81.101]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 20 Jul 2020 09:39:56 +0000 (GMT) Subject: Re: [RFC PATCH] powerpc/pseries/svm: capture instruction faulting on MMIO access, in sprg0 register To: Ram Pai , kvm-ppc@vger.kernel.org, linuxppc-dev@lists.ozlabs.org References: <1594888333-9370-1-git-send-email-linuxram@us.ibm.com> From: Laurent Dufour Message-ID: <18e3bcee-8a3a-bd13-c995-8e4168471f74@linux.ibm.com> Date: Mon, 20 Jul 2020 11:39:56 +0200 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <1594888333-9370-1-git-send-email-linuxram@us.ibm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-20_05:2020-07-17, 2020-07-20 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 mlxscore=0 phishscore=0 impostorscore=0 spamscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2007200071 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aik@ozlabs.ru, bharata@linux.ibm.com, sathnaga@linux.vnet.ibm.com, sukadev@linux.vnet.ibm.com, bauerman@linux.ibm.com, david@gibson.dropbear.id.au Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Le 16/07/2020 à 10:32, Ram Pai a écrit : > An instruction accessing a mmio address, generates a HDSI fault. This fault is > appropriately handled by the Hypervisor. However in the case of secureVMs, the > fault is delivered to the ultravisor. > > Unfortunately the Ultravisor has no correct-way to fetch the faulting > instruction. The PEF architecture does not allow Ultravisor to enable MMU > translation. Walking the two level page table to read the instruction can race > with other vcpus modifying the SVM's process scoped page table. > > This problem can be correctly solved with some help from the kernel. > > Capture the faulting instruction in SPRG0 register, before executing the > faulting instruction. This enables the ultravisor to easily procure the > faulting instruction and emulate it. > > Signed-off-by: Ram Pai > --- > arch/powerpc/include/asm/io.h | 85 ++++++++++++++++++++++++++++++++++++++----- > 1 file changed, 75 insertions(+), 10 deletions(-) > > diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h > index 635969b..7ef663d 100644 > --- a/arch/powerpc/include/asm/io.h > +++ b/arch/powerpc/include/asm/io.h > @@ -35,6 +35,7 @@ > #include > #include > #include > +#include > > #define SIO_CONFIG_RA 0x398 > #define SIO_CONFIG_RD 0x399 > @@ -105,34 +106,98 @@ > static inline u##size name(const volatile u##size __iomem *addr) \ > { \ > u##size ret; \ > - __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \ > - : "=r" (ret) : "Z" (*addr) : "memory"); \ > + if (is_secure_guest()) { \ > + __asm__ __volatile__("mfsprg0 %3;" \ > + "lnia %2;" \ > + "ld %2,12(%2);" \ > + "mtsprg0 %2;" \ > + "sync;" \ > + #insn" %0,%y1;" \ > + "twi 0,%0,0;" \ > + "isync;" \ > + "mtsprg0 %3" \ > + : "=r" (ret) \ > + : "Z" (*addr), "r" (0), "r" (0) \ I'm wondering if SPRG0 is restored to its original value. You're using the same register (r0) for parameters 2 and 3, so when doing lnia %2, you're overwriting the SPRG0 value you saved in r0 just earlier. It may be clearer to use explicit registers for %2 and %3 and to mark them as modified for the compiler. This applies to the other macros. Cheers, Laurent. > + : "memory"); \ > + } else { \ > + __asm__ __volatile__("sync;" \ > + #insn" %0,%y1;" \ > + "twi 0,%0,0;" \ > + "isync" \ > + : "=r" (ret) : "Z" (*addr) : "memory"); \ > + } \ > return ret; \ > } > > #define DEF_MMIO_OUT_X(name, size, insn) \ > static inline void name(volatile u##size __iomem *addr, u##size val) \ > { \ > - __asm__ __volatile__("sync;"#insn" %1,%y0" \ > - : "=Z" (*addr) : "r" (val) : "memory"); \ > - mmiowb_set_pending(); \ > + if (is_secure_guest()) { \ > + __asm__ __volatile__("mfsprg0 %3;" \ > + "lnia %2;" \ > + "ld %2,12(%2);" \ > + "mtsprg0 %2;" \ > + "sync;" \ > + #insn" %1,%y0;" \ > + "mtsprg0 %3" \ > + : "=Z" (*addr) \ > + : "r" (val), "r" (0), "r" (0) \ > + : "memory"); \ > + } else { \ > + __asm__ __volatile__("sync;" \ > + #insn" %1,%y0" \ > + : "=Z" (*addr) : "r" (val) : "memory"); \ > + mmiowb_set_pending(); \ > + } \ > } > > #define DEF_MMIO_IN_D(name, size, insn) \ > static inline u##size name(const volatile u##size __iomem *addr) \ > { \ > u##size ret; \ > - __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\ > - : "=r" (ret) : "m" (*addr) : "memory"); \ > + if (is_secure_guest()) { \ > + __asm__ __volatile__("mfsprg0 %3;" \ > + "lnia %2;" \ > + "ld %2,12(%2);" \ > + "mtsprg0 %2;" \ > + "sync;" \ > + #insn"%U1%X1 %0,%1;" \ > + "twi 0,%0,0;" \ > + "isync;" \ > + "mtsprg0 %3" \ > + : "=r" (ret) \ > + : "m" (*addr), "r" (0), "r" (0) \ > + : "memory"); \ > + } else { \ > + __asm__ __volatile__("sync;" \ > + #insn"%U1%X1 %0,%1;" \ > + "twi 0,%0,0;" \ > + "isync" \ > + : "=r" (ret) : "m" (*addr) : "memory"); \ > + } \ > return ret; \ > } > > #define DEF_MMIO_OUT_D(name, size, insn) \ > static inline void name(volatile u##size __iomem *addr, u##size val) \ > { \ > - __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \ > - : "=m" (*addr) : "r" (val) : "memory"); \ > - mmiowb_set_pending(); \ > + if (is_secure_guest()) { \ > + __asm__ __volatile__("mfsprg0 %3;" \ > + "lnia %2;" \ > + "ld %2,12(%2);" \ > + "mtsprg0 %2;" \ > + "sync;" \ > + #insn"%U0%X0 %1,%0;" \ > + "mtsprg0 %3" \ > + : "=m" (*addr) \ > + : "r" (val), "r" (0), "r" (0) \ > + : "memory"); \ > + } else { \ > + __asm__ __volatile__("sync;" \ > + #insn"%U0%X0 %1,%0" \ > + : "=m" (*addr) : "r" (val) : "memory"); \ > + mmiowb_set_pending(); \ > + } \ > } > > DEF_MMIO_IN_D(in_8, 8, lbz); >