From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from py-out-1112.google.com (py-out-1112.google.com [64.233.166.181]) by ozlabs.org (Postfix) with ESMTP id 746D867BAE for ; Wed, 6 Sep 2006 10:50:08 +1000 (EST) Received: by py-out-1112.google.com with SMTP id t32so3396528pyc for ; Tue, 05 Sep 2006 17:50:07 -0700 (PDT) Message-ID: <198592450609051750r70f94750n363e2389f82e3698@mail.gmail.com> Date: Wed, 6 Sep 2006 00:50:07 +0000 From: "Reeve Yang" To: linuxppc-embedded@ozlabs.org Subject: Re: MPC8245 reset register In-Reply-To: <53107f6e0609051706i67eac762y114ad03bf2065548@mail.gmail.com> MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_122005_27194957.1157503807711" References: <198592450609021546x57c71e48r9aed561b61f6e8aa@mail.gmail.com> <53107f6e0609021647l1f1cd84du496e3cd7219b603@mail.gmail.com> <198592450609051149h47423ebev9c94eb8aefc2a3fb@mail.gmail.com> <53107f6e0609051706i67eac762y114ad03bf2065548@mail.gmail.com> List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , ------=_Part_122005_27194957.1157503807711 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline LoL, my bad not understanding the humor. This becomes an interesting topic. I looked at different CPUs, it seems everyone uses different method to reset itself, and there is no uniformed or easy for 603e. I searched on google but didn't see anyone have similiar concern. Actually lots of boxes/systems using MPC8245, why nobody cares about it? :) To use watchdog timeout, or gpio port to assert reset line on CPU are not flexible enough. If using watchdog, I have to enable watchdog and reduce the timeout length (if it's too long). If using some GPIO device, I'll have to rely on i2c bus or whatever io interface to write data. Acutally our system has RESET by a GPIO(PCA9556) port. Interesting enough, I resolved the problem by writing a data to an invalid address with hoping for a machine check exception (in fact this is what u-boot does). Would it be good to make it as a stardard "restart" function in mpc10x_common.c? If it's acceptable I could send out my patch. - Reeve On 9/6/06, Jon Scully wrote: > > On 9/5/06, Reeve Yang wrote: > > I'm kind of curious what's the proper way to reset the > > 8245 CPU? For anyone who doesn't know MPC8245, which is 603e core. > > You could starve the watchdog (assuming SWE=1 in SYPCR). If you own > the hardware design, you could add an addressable WO latch (FPGA) that > asserts reset for the right number of clock cycles (what I would > normally provide or ask for in a design -- but *only* during > development). Otherwise... If this is for development purposes, > consider using JTAG (Boundary Scan) to control /SRESET. > > (My reference to RST was supposed to be humorous -- as in, remember > the good old days when you could do that in S/W?! ('RST 7' in Z80 & > 8085) Sorry for my bad humor.) > _______________________________________________ > Linuxppc-embedded mailing list > Linuxppc-embedded@ozlabs.org > https://ozlabs.org/mailman/listinfo/linuxppc-embedded > ------=_Part_122005_27194957.1157503807711 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline LoL, my bad not understanding the humor.

This becomes an interesting topic. I looked at different CPUs, it seems everyone uses different method to reset itself, and there is no uniformed or easy for 603e. I searched on google but didn't see anyone have similiar concern. Actually lots of boxes/systems using MPC8245, why nobody cares about it? :)

To use watchdog timeout, or gpio port to assert reset line on CPU are not flexible enough. If using watchdog, I have to enable watchdog and reduce the timeout length (if it's too long). If using some GPIO device, I'll have to rely on i2c bus or whatever io interface to write data. Acutally our system has RESET by a GPIO(PCA9556) port.

Interesting enough, I resolved the problem by writing a data to an invalid address with hoping for a machine check exception (in fact this is what u-boot does). Would it be good to make it as a stardard "restart" function in mpc10x_common.c? If it's acceptable I could send out my patch.

- Reeve

On 9/6/06, Jon Scully <jonscully@gmail.com> wrote:
On 9/5/06, Reeve Yang <yang.reeve@gmail.com> wrote:
>  I'm kind of curious what's the proper way to reset the
> 8245 CPU? For anyone who doesn't know MPC8245, which is 603e core.

You could starve the watchdog (assuming SWE=1 in SYPCR).  If you own
the hardware design, you could add an addressable WO latch (FPGA) that
asserts reset for the right number of clock cycles (what I would
normally provide or ask for in a design -- but *only* during
development).  Otherwise... If this is for development purposes,
consider using JTAG (Boundary Scan) to control /SRESET.

(My reference to RST was supposed to be humorous -- as in, remember
the good old days when you could do that in S/W?! ('RST 7' in Z80 &
8085)  Sorry for my bad humor.)
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