L2CR

L2CR

[Kyle Nesbit]

I am currently looking for some more info on how to get my L2 backside cache
running.  I am using a powerlogix card.

I have used the powerlogix/Ben patch posted in the mailing list during Dec.
The kernel compiled without and error.  When I try to pass the l2cr kernel
argument I get nothing.  my /proc/sys/kernel/l2cr is 00000000: disabled,
etc...

Another thing that is strange is in /proc/cpuinfo the clock rate of my chip
is off by over 100 MHZ.

I would greatly appreciate if someone could point me to more info on the
subject.

Thanx,
Kyle

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Re: L2CR

[BenH]

The up-to-date l2cr code should be in vger now, we disabled the
command-line option for now (it required changes in non-arch specific
sources, and we wanted to avoid this because of the merge). The l2cr
value can still be passed by BootX using the device-tree. Just open bootx
preferences with resedit, add an "L2CR" resource ID 0 which is 4 bytes
long, and stuff your L2CR value in it. This will enable the "Set G3
cache" option in BootX.

Future version of PowerLogix software may be able to set BootX
Preferences directly. I'll write a tool for capturing MacOS current L2CR
value real soon now.


On Mon, Feb 8, 1999, Kyle Nesbit <kyle.nesbit@asu.edu> wrote:

>I am currently looking for some more info on how to get my L2 backside cache
>running.  I am using a powerlogix card.
>
>I have used the powerlogix/Ben patch posted in the mailing list during Dec.
>The kernel compiled without and error.  When I try to pass the l2cr kernel
>argument I get nothing.  my /proc/sys/kernel/l2cr is 00000000: disabled,
>etc...
>
>Another thing that is strange is in /proc/cpuinfo the clock rate of my chip
>is off by over 100 MHZ.
>
>I would greatly appreciate if someone could point me to more info on the
>subject.


-- 
           E-Mail: <mailto:bh40@calva.net>
BenH.      Web   : <http://calvaweb.calvacom.fr/bh40/>





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Re: L2CR

[BenH]

At this URL:

<ftp://ftp.linuxppc.org/development/users/benh/GrabG3CacheSetting.sit>

Is a little application that grabs the current L2CR setting under MacOS
and puts it in BootX prefs, enabling BootX "Set G3 Cache" option. The
L2CR value is then put in the device tree by BootX and retreived later by
the kernel.

You need a recent kernel for this to work (vger 2.2.x or Paul's ones) and
a recent version of BootX too:

<ftp://ftp.linuxppc.org/development/users/benh/BootX_1.0.2b1.sit>

This tools does a big horrible hack to get the L2CR value (thanks again
to Terry Greeniaus for the tips !) so I'm interested in any problem you
may encounter.

If that works, the kernel should print in the boot messages (look at
dmesg) a message like "L2CR overriden (value), backside cache is enabled\n"


-- 
           E-Mail: <mailto:bh40@calva.net>
BenH.      Web   : <http://calvaweb.calvacom.fr/bh40/>





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