From mboxrd@z Thu Jan  1 00:00:00 1970
Date: Tue, 26 Oct 1999 18:38:26 -0400
From: Tom Vier <thomassr@erols.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: linuxppc-dev@lists.linuxppc.org
Subject: Re: question about altivec registers
Message-ID: <19991026183826.A6668@zero>
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On Tue, Oct 26, 1999 at 08:22:06PM +0200, Geert Uytterhoeven wrote:

> Moving around blocks of 512 bytes quickly thrashes the L1 cache, unless the
> loads/stores are done using cache-bypassing instructions (cfr. MOVE16 on '040).
> Don't know whether PPC has these (still no PPC guru :-(

from what i've read, you can disable cache for the altivec regs. this was
intended for doing infrequent vector ops between frequent vectors ops
(loops) without distrubing the cache.

-- 
Tom Vier - 0x27371A1C
thomassr@erols.com
http://users.erols.com/thomassr/zero/

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