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Wed, 06 Oct 2021 19:25:09 -0700 (PDT) Received: from [10.230.29.137] ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id g23sm22285369pfu.71.2021.10.06.19.24.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 Oct 2021 19:25:08 -0700 (PDT) Message-ID: <1a15bbef-cf3d-33c6-b6c1-3dd607d71d1d@gmail.com> Date: Wed, 6 Oct 2021 19:24:50 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.1.2 Subject: Re: [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support Content-Language: en-US To: Rob Herring , Russell King , James Morse , Catalin Marinas , Will Deacon , Guo Ren , Jonas Bonn , Stefan Kristiansson , Stafford Horne , Michael Ellerman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Yoshinori Sato , Rich Felker , x86@kernel.org, Greg Kroah-Hartman References: <20211006164332.1981454-1-robh@kernel.org> From: Florian Fainelli In-Reply-To: <20211006164332.1981454-1-robh@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Scott Branden , "Rafael J. Wysocki" , linux-sh@vger.kernel.org, Ray Jui , "H. Peter Anvin" , linux-kernel@vger.kernel.org, linux-csky@vger.kernel.org, openrisc@lists.librecores.org, Ingo Molnar , Paul Mackerras , Borislav Petkov , bcm-kernel-feedback-list@broadcom.com, Thomas Gleixner , Frank Rowand , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 10/6/2021 9:43 AM, Rob Herring wrote: > The first 10 patches add a new function, of_get_cpu_hwid(), which parses > CPU DT node 'reg' property, and then use it to replace all the open > coded versions of parsing CPU node 'reg' properties. > > The last 2 patches add support for populating the cacheinfo 'id' on DT > platforms. The minimum associated CPU hwid is used for the id. The id is > optional, but necessary for resctrl which is being adapted for Arm MPAM. > > Tested on arm64. Compile tested on arm, x86 and powerpc. On ARM and ARM64: Tested-by: Florian Fainelli lscpu -C continues to work on ARM64 as before with cache properties provided in the FDT. -- Florian