From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from py-out-1112.google.com (py-out-1112.google.com [64.233.166.183]) by ozlabs.org (Postfix) with ESMTP id 4F58267BE1 for ; Wed, 25 Oct 2006 17:23:05 +1000 (EST) Received: by py-out-1112.google.com with SMTP id f25so55254pyf for ; Wed, 25 Oct 2006 00:23:04 -0700 (PDT) Message-ID: <1b2aacd80610250016q4bcc5f9bm467ef09022ce1285@mail.gmail.com> Date: Wed, 25 Oct 2006 00:16:41 -0700 From: "Luong Ngo" To: "Kumar Gala" Subject: Re: MPC8343: PCI resource allocation questions In-Reply-To: <4BF669F6-7A28-4915-9DFF-0B00CC04E242@kernel.crashing.org> MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_Part_105401_22840958.1161760601233" References: <1b2aacd80610242049j23917f61x1e277b4c6a581f9a@mail.gmail.com> <1b2aacd80610242246n20075a33pcc76ab5be71fb87e@mail.gmail.com> <4BF669F6-7A28-4915-9DFF-0B00CC04E242@kernel.crashing.org> Cc: linuxppc-dev list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , ------=_Part_105401_22840958.1161760601233 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline Would you mind explain me the last question in previous email? You are not leaving any memory space for any of the onchip devices, the error messages are because the regions of memory that the devices are expected to be at are already occupied by the PCI space. Isn't it the PCI IO and PCI MEM space are separated from local memory space? I think I see the global IO resource and MEM resource have the range of 0x0 - 0xFFFFFFFF. Thanks, Luong Ngo On 10/24/06, Kumar Gala wrote: > > > > I'm a bit confused here. If the host bridge is ignored/excluded, > > then the region size in BARs will not be allocated corresponding > > resource by the PCI subsystem, then how would other PCI devices in > > the slots could be allocated in the BAR's range? If I understand > > correctly, the PCI devices's resources are allocated based on the > > bridge resource, which is assigned statically by PCI subsystem > > using hose->mem_space and hose->io_space instead of reading it from > > the BARs. Maybe you are saying in the case the CPU is in agent mode > > and its PCI host bridge is functioning as a PCI-PCI bridge? > > The problem is the host bridge shouldn't be included in BAR > assignment since its the host bridge. The problem is FSL devices > show up when they scan themselves and the kernel then tries to > allocate resources to them as if they were any other device. > > you are correct, the pci subsystem is setup via the hose structure > and not by trying to read BARs on the host controller itself. > > - kumar > ------=_Part_105401_22840958.1161760601233 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline

Would you mind explain me the last question in previous email?
 
 
You are not leaving any memory space for any of the onchip devices,
the error messages are because the regions of memory that the devices
are expected to be at are already occupied by the PCI space.
 
Isn't it the PCI IO and PCI MEM space are separated from local memory space? I think I see the global IO resource and MEM resource have the range of 0x0 - 0xFFFFFFFF.
 
Thanks,
Luong Ngo
 
On 10/24/06, Kumar Gala <galak@kernel.crashing.org> wrote:

> I'm a bit confused here. If the host bridge is ignored/excluded,
> then the region size in BARs will not be allocated corresponding
> resource by the PCI subsystem, then how would other PCI devices in
> the slots could be allocated in the BAR's range? If I understand
> correctly, the PCI devices's resources are allocated based on the
> bridge resource, which is assigned statically by PCI subsystem
> using hose->mem_space and hose->io_space instead of reading it from
> the BARs. Maybe you are saying in the case the CPU is in agent mode
> and its PCI host bridge is functioning as a PCI-PCI bridge?

The problem is the host bridge shouldn't be included in BAR
assignment since its the host bridge.  The problem is FSL devices
show up when they scan themselves and the kernel then tries to
allocate resources to them as if they were any other device.

you are correct, the pci subsystem is setup via the hose structure
and not by trying to read BARs on the host controller itself.

- kumar

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