Re: 8544 external interrupt configuration problems

[Nancy Isaac <nancy.isaac@pobox.com>]

[-- Attachment #1: Type: text/plain, Size: 3237 bytes --]

Thank you for your response.  My responses below.

On Thu, May 28, 2009 at 1:02 PM, Scott Wood <scottwood@freescale.com> wrote:

> On Thu, May 28, 2009 at 12:05:52PM -0700, Nancy Isaac wrote:
> > My device tree has the following entry for my fpga:
> >
> > CpuCpld\@f0000000{
> >                         compatible = "MPC8544DS";
> >                         device_type = "CpuCpld";
> >                         reg = <f0000000 00000040>;
> >                         interrupts = <41 2 42 2 43 2>;
> >                         interrupt-parent = <&mpic>;
> > };
>
> Where did you get those interrupt numbers from?  External interrupt
> numbers start at zero on MPIC.


<NI> I  tried several  things and this is the last set I tried. These
numbers start at the end of the internal interrupts.

I also tried specifying 1, 2 and 3 because it looks like there is just an
array of these interrupts and the interrupts are just added to this array as
they are registered with the hwirq and the virq is the index into the array
where the hwirq was added.  I get slightly different results but still not
accurate.

For example, in the device tree, I had setup interrupts = <1 2 2 2 3 2>; for
irq1, 2 and 3 which are all level sensitive interrupts. These map to virq
0x12, 0x13 and 0x14 .  I verify that there is no interrupt present by
looking at the registers in the FPGA and also by connecting a scope to the
signal.  Immediately after I finish registering the irqs listed above, I get
an interrupt  and my print statement in the do_IRQ function returns irq
number 0x12.  This happens even if I've disabled the interrupt at the FPGA.
Then I forced an interrupt to occur at the FPGA on irq2 and the do_irq
function still reports that the irq occured for 0x12.

>
> Is the level/sense information correct?


[NI] Yes, these interrupts are supposed to be active low, level sensitive
interrupts.


> > My driver does the mapping to the virq:
> >
> >  np = of_find_node_by_type(NULL, "CpuCpld");
> >     if (!np) {
> >         ret = -ENODEV;
> >     }
> >     cpldCpuDrv->MateIntIrq = irq_of_parse_and_map(np, 0);
> >     cpldCpuDrv->FtaIrq =  irq_of_parse_and_map(np, 1);
> >     cpldCpuDrv->ExtractIrq =  irq_of_parse_and_map(np, 2);
> >     cpldCpuDrv->XauiIrq =  irq_of_parse_and_map(np, 0);
> >
> >     of_node_put(np);
>
> Looks good (other than that you should be using compatible (with a more
> specific name) rather than device_type).
>
> > Does anyone know what the virq should be for these external interrupts?
>
> They're dynamically assigned.
>
> > I've tried specifying the actual irq numbers 1,2 and 3 and that doesn't
> work
> > either.
>
> Specifying them where?  In the device tree or as virq numbers?  Never
> hard-code virq numbers.


[NI] I specify this in the device tree.

>
>
> > Is there some PCI configuration that's getting in the way?  I've tried
> > disabling the FSL_PCIE and I get the same behavior.
>
> Barring an unusual bug, PCI should have nothing to do with the interrupt
> routing of things that aren't on the PCI bus.


[NI]. For 8544, the external interrupts can be shared with PCI Express. I
thought that if I am somehow enabling PCI Express, maybe it would explain
this behavior.


>
>
> -Scott
>

Thanks
Nancy

[-- Attachment #2: Type: text/html, Size: 4659 bytes --]