Fwd: [FSL P50x0] Keyboard and mouse don't work anymore after the devicetree updates for 5.19

[Christian Zigotzky <chzigotzky@xenosoft.de>]

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Rob's email address corrected.

-- Christian


On 27 May 2022 at 09:23 am, Christophe Leroy wrote:
> Hi
>
> Le 26/05/2022 à 19:42, Christian Zigotzky a écrit :
>> Hello,
>>
>> My keyboard and mouse don't work anymore with my Cyrus+ board with a FSL
>> P50x0 PowerPC SoC [1] after the devicetree updates for 5.19 [2].
>> After reverting the devicetree updates, my keyboard and mouse work
>> without any problems.
>> I figured out that the issue is in the patch for the file platform.c
>> [3].  I created a patch for reverting the problematic code. (see
>> attachment)
>> After reverting the changes with the attached patch, the keyboard and
>> mouse work again.
>> Please check your changes in the file platform.c [3].
>>
>> Thanks,
>> Christian
>>
>> [1] http://wiki.amiga.org/index.php?title=X5000
>> [2]
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=86c87bea6b42100c67418af690919c44de6ede6e
>>
>> [3]
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/diff/drivers/of/platform.c?id=86c87bea6b42100c67418af690919c44de6ede6e
>
> Based on your patch I would say the culprit commit is
> https://github.com/torvalds/linux/commit/a1a2b7125e1079cfcc13a116aa3af3df2f9e002b
>
> commit a1a2b7125e1079cfcc13a116aa3af3df2f9e002b
> Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Date: Wed Mar 16 20:06:33 2022 +0000
>
> of/platform: Drop static setup of IRQ resource from DT core
>
> Now that all the DT drivers have switched to platform_get_irq() we
> can now
> safely drop the static setup of IRQ resource from DT core code.
>
> With the above change hierarchical setup of irq domains is no longer
> bypassed and thus allowing hierarchical interrupt domains to describe
> interrupts using "interrupts" DT property.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Acked-by: Marc Zyngier <maz@kernel.org>
> Tested-by: Marc Zyngier <maz@kernel.org>
> Signed-off-by: Rob Herring <robh@kernel.org>
> Link:
> https://lore.kernel.org/r/20220316200633.28974-1-prabhakar.mahadev-lad.rj@bp.renesas.com
>
>
>
> Can you please provide you device tree ?
>
> Do you use any out-of-tree drivers ?
>
> Thanks
> Christophe
Hi Christophe,

No, I don't use any out-of-tree drivers. Please find attached the dtb, 
dts, and the dtsi file.

Thanks,
Christian

[-- Attachment #2: p5040si-pre.dtsi --]
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/*
 * P5040 Silicon/SoC Device Tree Source (pre include)
 *
 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * This software is provided by Freescale Semiconductor "as is" and any
 * express or implied warranties, including, but not limited to, the implied
 * warranties of merchantability and fitness for a particular purpose are
 * disclaimed. In no event shall Freescale Semiconductor be liable for any
 * direct, indirect, incidental, special, exemplary, or consequential damages
 * (including, but not limited to, procurement of substitute goods or services;
 * loss of use, data, or profits; or business interruption) however caused and
 * on any theory of liability, whether in contract, strict liability, or tort
 * (including negligence or otherwise) arising in any way out of the use of this
 * software, even if advised of the possibility of such damage.
 */

/dts-v1/;

/include/ "e5500_power_isa.dtsi"

/ {
	compatible = "fsl,P5040";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	aliases {
		ccsr = &soc;
		dcsr = &dcsr;

		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serial3;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
		usb0 = &usb0;
		usb1 = &usb1;
		dma0 = &dma0;
		dma1 = &dma1;
		sdhc = &sdhc;
		msi0 = &msi0;
		msi1 = &msi1;
		msi2 = &msi2;

		crypto = &crypto;
		sec_jr0 = &sec_jr0;
		sec_jr1 = &sec_jr1;
		sec_jr2 = &sec_jr2;
		sec_jr3 = &sec_jr3;
		rtic_a = &rtic_a;
		rtic_b = &rtic_b;
		rtic_c = &rtic_c;
		rtic_d = &rtic_d;
		sec_mon = &sec_mon;

		raideng = &raideng;
		raideng_jr0 = &raideng_jr0;
		raideng_jr1 = &raideng_jr1;
		raideng_jr2 = &raideng_jr2;
		raideng_jr3 = &raideng_jr3;

		fman0 = &fman0;
		fman1 = &fman1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: PowerPC,e5500@0 {
			device_type = "cpu";
			reg = <0>;
			clocks = <&clockgen 1 0>;
			next-level-cache = <&L2_0>;
			fsl,portid-mapping = <0x80000000>;
			L2_0: l2-cache {
				next-level-cache = <&cpc>;
			};
		};
		cpu1: PowerPC,e5500@1 {
			device_type = "cpu";
			reg = <1>;
			clocks = <&clockgen 1 1>;
			next-level-cache = <&L2_1>;
			fsl,portid-mapping = <0x40000000>;
			L2_1: l2-cache {
				next-level-cache = <&cpc>;
			};
		};
		cpu2: PowerPC,e5500@2 {
			device_type = "cpu";
			reg = <2>;
			clocks = <&clockgen 1 2>;
			next-level-cache = <&L2_2>;
			fsl,portid-mapping = <0x20000000>;
			L2_2: l2-cache {
				next-level-cache = <&cpc>;
			};
		};
		cpu3: PowerPC,e5500@3 {
			device_type = "cpu";
			reg = <3>;
			clocks = <&clockgen 1 3>;
			next-level-cache = <&L2_3>;
			fsl,portid-mapping = <0x10000000>;
			L2_3: l2-cache {
				next-level-cache = <&cpc>;
			};
		};
	};
};

[-- Attachment #3: cyrus_p5040.dts --]
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/*
 * Cyrus 5040 Device Tree Source, based on p5040ds.dts
 *
 * Copyright 2020 Darren Stevens
 *
 * p5040ds.dts Copyright 2012 - 2015 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * This software is provided by Freescale Semiconductor "as is" and any
 * express or implied warranties, including, but not limited to, the implied
 * warranties of merchantability and fitness for a particular purpose are
 * disclaimed. In no event shall Freescale Semiconductor be liable for any
 * direct, indirect, incidental, special, exemplary, or consequential damages
 * (including, but not limited to, procurement of substitute goods or services;
 * loss of use, data, or profits; or business interruption) however caused and
 * on any theory of liability, whether in contract, strict liability, or tort
 * (including negligence or otherwise) arising in any way out of the use of this
 * software, even if advised of the possibility of such damage.
 */

/include/ "p5040si-pre.dtsi"

/ {
	model = "varisys,CYRUS5040";
	compatible = "varisys,CYRUS";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	aliases{
		ethernet0 = &enet4;
		ethernet1 = &enet10;
	};

	memory {
		device_type = "memory";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		bman_fbpr: bman-fbpr {
			size = <0 0x1000000>;
			alignment = <0 0x1000000>;
		};
		qman_fqd: qman-fqd {
			size = <0 0x400000>;
			alignment = <0 0x400000>;
		};
		qman_pfdr: qman-pfdr {
			size = <0 0x2000000>;
			alignment = <0 0x2000000>;
		};
	};

	dcsr: dcsr@f00000000 {
		ranges = <0x00000000 0xf 0x00000000 0x01008000>;
	};

	bportals: bman-portals@ff4000000 {
		ranges = <0x0 0xf 0xf4000000 0x200000>;
	};

	qportals: qman-portals@ff4200000 {
		ranges = <0x0 0xf 0xf4200000 0x200000>;
	};

	soc: soc@ffe000000 {
		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
		reg = <0xf 0xfe000000 0 0x00001000>;
		spi@110000 {
		};

		i2c@118100 {
		};

		i2c@119100 {
			rtc@6f {
				compatible = "microchip,mcp7941x";
				reg = <0x6f>;
			};
		};

		gpio-poweroff {
			compatible = "gpio-poweroff";
			gpios = <&gpio0 3 1>;
		};

		gpio-restart {
			compatible = "gpio-restart";
			gpios = <&gpio0 2 1>;
		};

		leds {
			compatible = "gpio-leds";
			hdd {
				label = "Disk activity";
				gpios = <&gpio0 5 0>;
				linux,default-trigger = "disk-activity";
			};
		};

		fman@400000 {
			mdio@e1120 {
				phy3: ethernet-phy@3 {
					reg = <0x3>;
				};

				phy7: ethernet-phy@7 {
					reg = <0x7>;
				};
			};

			ethernet@e0000 {
				status = "disabled";
			};

			ethernet@e2000 {
				status = "disabled";
			};

			ethernet@e4000 {
				status = "disabled";
			};

			ethernet@e6000 {
				status = "disabled";
			};

			ethernet@e8000 {
				phy-handle = <&phy3>;
				phy-connection-type = "rgmii";
			};

		};

		fman@500000 {
			ethernet@e0000 {
				status = "disabled";
			};

			ethernet@e2000 {
				status = "disabled";
			};

			ethernet@e4000 {
				status = "disabled";
			};

			ethernet@e6000 {
				status = "disabled";
			};

			ethernet@e8000 {
				phy-handle = <&phy7>;
				phy-connection-type = "rgmii";
			};

		};

	};

	lbc: localbus@ffe124000 {
		reg = <0xf 0xfe124000 0 0x1000>;
		ranges = <0 0 0xf 0xe8000000 0x08000000
			  2 0 0xf 0xffa00000 0x00040000
			  3 0 0xf 0xffdf0000 0x00008000>;

	};

	pci0: pcie@ffe200000 {
		reg = <0xf 0xfe200000 0 0x1000>;
		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci1: pcie@ffe201000 {
		reg = <0xf 0xfe201000 0 0x1000>;
		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};

	pci2: pcie@ffe202000 {
		reg = <0xf 0xfe202000 0 0x1000>;
		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
		pcie@0 {
			ranges = <0x02000000 0 0xe0000000
				  0x02000000 0 0xe0000000
				  0 0x20000000

				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00010000>;
		};
	};
};

/include/ "p5040si-post.dtsi"

[-- Attachment #4: cyrus-p5040.dtb --]
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