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Fri, 31 Jul 2026 17:57:13 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (smtpav02.fra02v.mail.ibm.com [10.20.54.101]) by smtprelay01.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 66VHvB6w30540242 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 31 Jul 2026 17:57:11 GMT Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 776B520040; Fri, 31 Jul 2026 17:57:11 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 31BBB20043; Fri, 31 Jul 2026 17:57:09 +0000 (GMT) Received: from [9.124.209.55] (unknown [9.124.209.55]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 31 Jul 2026 17:57:08 +0000 (GMT) Message-ID: <1eab63fc-b70d-41ef-b720-8ae77d8e56d8@linux.ibm.com> Date: Fri, 31 Jul 2026 23:27:06 +0530 X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 1/1] powerpc: enable dynamic preemption To: Jirka Hladky Cc: "Christophe Leroy (CS GROUP)" , paulmck@kernel.org, maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org, mpe@ellerman.id.au, npiggin@gmail.com, bigeasy@linutronix.de, will@kernel.org, linux-kernel@vger.kernel.org References: <500d8e8c-088c-4e6d-ab53-868ade6b0eda@paulmck-laptop> <29a407ab-268e-4443-96dc-8f5f933cb63c@linux.ibm.com> <529b8d9f-54a0-4ec2-9886-83cd528e5e04@paulmck-laptop> <57d9de4a-65aa-44cf-9024-de4e5bdd1971@linux.ibm.com> <972db4f1-406b-477b-895e-59ffc643e384@kernel.org> <4be922b5-7dc2-48c1-938c-de02245bc5e2@linux.ibm.com> Content-Language: en-US From: Shrikanth Hegde In-Reply-To: Content-Type: text/plain; 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On 7/31/26 7:20 PM, Jirka Hladky wrote: > On Fri, Jul 31, 2026 at 10:03 AM Shrikanth Hegde wrote: >> Coming into numbers, I did notice later, arm64 numbers are almost 20x less. >> But if we compare the time taken for each operations, it tells a >> different story. > > The bottom line: PREEMPT_DYNAMIC/preempt_count overhead is present > on both RISC architectures but its visibility depends heavily on the > workload profile and hardware topology. > >> PS: I tried porting some of those changes in arm64 to powerpc to >> split preempt count into two. but i don;t see much improvement >> there. I tried moving to PACA plus splitting 64 bit into need_resched and preempt count. But it doesn;t move the needle. But it maybe worth pursuing, since it could help preemption modes. It needs more work and needs numbers across benchmark. > > Thanks for trying. Paul questioned whether barriers are actually > needed for preempt_count, or whether software interrupt disabling > would suffice (his words: "I can see why the preempt_count() > operations need to be interrupt-safe, but I don't see why you would > need barriers"). Any thoughts on whether that's feasible for > powerpc? > Barrier are likely not the concern as it is mostly nop. Also, soft disabling interrupts needs to arch specific hooks to setup before preempt_disable and replay interrupts after preempt_enable. I don't think it would benefit since interrupt disabling during this likely shouldn't happen. Maybe I don't understand how that could work.