From mboxrd@z Thu Jan  1 00:00:00 1970
In-Reply-To: <Pine.HPX.4.10.10001211502220.18916-100000@gra-ux1.iram.es>
Date: Fri, 21 Jan 2000 16:29:56 +0100
To: Gabriel Paubert <paubert@iram.es>, linuxppc-dev@lists.linuxppc.org
From: Benjamin Herrenschmidt <bh40@calva.net>
Subject: Re: Fwd: Re: still no accelerated X ($#!$*)
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On Fri, Jan 21, 2000, Gabriel Paubert <paubert@iram.es> wrote:

>Bridges also may reorder writes and burst them, eieio can be used to
>prevent this. That's not only the processor effect...

My understanding of the PCI spec is that bridges are not allowed to
re-order. They an combine for burst but they are forbidden to do any
reordering.


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