From: Michel Lanners <mlan@mcp.cpu.lu>
To: nicoya@apia.dhs.org (Tony Mantler)
Cc: mlan@cpu.lu, drow@false.org, linuxppc-dev@lists.linuxppc.org
Subject: Re: [patch] VRAM detection in controlfb
Date: Mon, 05 Jun 2000 15:51:47 METDST [thread overview]
Message-ID: <200006051351.PAA19854@mcp.cpu.lu> (raw)
In-Reply-To: <v04003a00b5614aa89cff@[24.66.67.194]>; from "Tony Mantler" at Jun 5, 100 7:40 am
Hi all,
[about caching and framebuffers]
> I'm not sure of the design specifics of the Control video, but most of the
> Apple video designs I've seen put the high-bandwidth low-latency video ram
> right on the main bus, so it's already half way to being a cache in and of
> itself (I seem to recall apple's sound manager using vram for buffer
> space), and would benefit very little from the CPU cache, except perhaps in
> a multi-cpu machine to keep bus chatter down to a minimum, but the exact
> tradeoffs of that would take a bit of consideration to quantify.
In the case of control, the VRAM seems to be the same basic type as main
RAM (i.e. 60/70ns DRAM), and it is conceptually behind a PCI bridge. So
by itself it is not faster than main RAM....
> Besides that, unlike main ram, what has and hasn't been written back to the
> framebuffer makes a big difference in what you see on screen. Caching would
> probably make for some mighty weird flicker, jumpy or inconsistent video
> playback, and all sorts of evil visual gremlins. You could always cache the
> framebuffer as write-through, but then any value you might have got from
> the caching goes right out the window, as framebuffer writes should
> outnumber framebuffer reads by an order of magnitude.
The main reason for marking the VRAM cacheable (_how_ is a different story)
would be so that the CPU can burst to it; the net result being (as I have
understood it, but I may be wrong) that the CPU can fill the PCI bridge's
buffer with fast burst writes, and let the bridge take care of getting
the data to VRAM. According to Apple's doc on their PCI implementation,
all address space excpet main RAM is marked uncacheable by default, but
only cacheable space gets bursted to by the CPU.
So I guess the optimum would be to mark the VRAM cacheable, but in a way that
writes don't go into the cache. Would that be write-through?
> Anyways, that's the long answer. The short answer is: no, you probably
> don't want to cache the framebuffer.
Except for the above reasons ;-)
Cheers
Michel
-------------------------------------------------------
.sig enjoying a day off
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2000-06-05 13:51 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2000-05-31 22:43 [patch] VRAM detection in controlfb Michel Lanners
2000-06-01 0:57 ` Takashi Oe
2000-06-03 6:28 ` Michel Lanners
2000-06-03 7:13 ` Takashi Oe
2000-06-03 7:30 ` Geert Uytterhoeven
2000-06-03 8:49 ` Michel Dänzer
2000-06-03 9:22 ` Geert Uytterhoeven
2000-06-06 19:25 ` Michael Schmitz
2000-06-06 21:52 ` Michel Lanners
2000-06-03 7:38 ` Geert Uytterhoeven
2000-06-05 6:01 ` Michel Lanners
2000-06-04 0:09 ` Daniel Jacobowitz
2000-06-04 0:31 ` Ani Joshi
2000-06-04 13:55 ` Michel Lanners
2000-06-05 12:59 ` Michel Dänzer
2000-06-03 9:16 ` Franz Sirl
2000-06-04 7:09 ` Michel Lanners
2000-06-04 15:08 ` Tony Mantler
2000-06-04 17:48 ` Daniel Jacobowitz
2000-06-05 5:48 ` Michel Lanners
2000-06-05 12:40 ` Tony Mantler
2000-06-05 13:51 ` Michel Lanners [this message]
2000-06-05 14:15 ` Geert Uytterhoeven
2000-06-05 23:49 ` Tony Mantler
2000-06-06 5:15 ` Timothy A. Seufert
2000-06-06 19:49 ` Michael Schmitz
2000-06-06 21:58 ` Michel Lanners
2000-06-07 7:59 ` Geert Uytterhoeven
[not found] <20000607233456Z.roikawa@rr.iij4u.or.jp>
2000-06-07 15:10 ` Geert Uytterhoeven
2000-06-07 15:20 ` Michael Schmitz
2000-06-07 15:41 ` Geert Uytterhoeven
2000-06-07 15:58 ` Ryuichi Oikawa
2000-06-07 19:11 ` Geert Uytterhoeven
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