Fighting with Sonnet g3/l2 upgrade

Fighting with Sonnet g3/l2 upgrade

[Keith Clayton]

Ben,

If you're out there, this question is directed toward you though anyone can
chime in.

A bit of quick history first.  Just installed a 400mhz Sonnet g3/l2 upgrade
into my umax c500.  Card is working in MacOS.  When booting via bootx I get
hda: lost interrupts.  Tried bootx versions between 1.1.3 and 1.2.2  Tried
my own kernel (2.2.18pre18) and precompiled kernels 2.2.12, 2.2.18-4hpmac
2.2.17-0.6.1 from yd site.  In all cases, same problem.  One thing that is
constant throughout is that under options for BootX the Set G3 Cache option
stays grey'd out.  Oh, Crescendo extension changed to type scri and renamed
to load before BootX.  I've tried using Cache Profiler loading after
Crescendo but before BootX with configure BootX option both on and off.

In every case, I get hda: lost interrupt

Ok, history done . . now . . I tried the G3 Cache Utility and it failed.  Said
not a G3 family processor.  I looked at the source and saw it was failing at
the cpuFamily != getstalt750 line.  So looks like the problem is that the
system isn't reporting back that a g3 is running.

A look at the bootx source shows that the Set G3 cache option will be
available only if the gestalt returns with a g3 processor.

Now my questions . . is it possible to modify the GrabG3Cache util to print
out the gestalt result to see what processor type is reported, then skip the
cpu family check so that the util proceeds and see what happens?  I'd do it
myself but I don't have CodeWarrior (or any compiler on the Mac side for that
matter).

Also, while this is probably a BAD idea, is it possible to create a BootX build
where the g_l2cr_available (i think that's right) flag is set to true from the
start so that the Set G3 cache option is available for me?  Using the
powerlogix util I can find the G3 Cache value and I can use resedit to set it
by hand in the BootX Settings file. Then maybe have a bunch of debugging
output or something.

I don't expect this to be a magic bullet or anything but I'm hoping to
understand where things are going wrong and see if it can be worked around.

Sorry to bug you Ben . . if I had CodeWarrior myself, I'd be able to do more
experimentation myself first.


Thanks for any help.  I'm sure your busy but if you could slide in a build,
that'd be fantastic.

Keith Clayton



--
<><><><><><><><><><><><>
Keith Clayton
clay-ton@pacbell.net

"If you don't trust me with your source code,
            why should I trust you with my computer?"

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Re: Fighting with Sonnet g3/l2 upgrade

[Benjamin Herrenschmidt]

>Also, while this is probably a BAD idea, is it possible to create a BootX
>build
>where the g_l2cr_available (i think that's right) flag is set to true
from the
>start so that the Set G3 cache option is available for me?  Using the
>powerlogix util I can find the G3 Cache value and I can use resedit to set it
>by hand in the BootX Settings file. Then maybe have a bunch of debugging
>output or something.
>
>I don't expect this to be a magic bullet or anything but I'm hoping to
>understand where things are going wrong and see if it can be worked around.
>
>Sorry to bug you Ben . . if I had CodeWarrior myself, I'd be able to do more
>experimentation myself first.

The hda: lost interrupt problems and the G3/L2 cache issues are 2
different things.

Is your Sonet card also providing an IDE interface ? In this case, it's
possible that the chipset on this card is not supported by 2.2.18 without
the big IDE patch (which need to be fixed for powerpc).

For the G3, I'd rather figure out the correct L2CR value and "fix" it
from userland (via /proc)

Ben.

** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/

Re: Fighting with Sonnet g3/l2 upgrade

[Keith Clayton]

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Nope, the Sonnet card isn't providing an IDE interface.  But that got me
thinking.  Is it possible that the l2 card is grabbing the interrupt in
question? Is there some way to check what interrupt values are being used
in the MacOS?  I can't check the Sonnet card in linux b/c linux won't boot
with it activated.  I do know that my ide interface is using interrupt 13.

Ohare based bridge.  I did some checking in the ide-pmac.c code and it
it appears that 13 is "picked out of the air".  Could this be the source of
the problem . . that the card utilizes an interrupt that matches the ide
interface?  Since the card isn't on the pci bus any sort of resource
management is out the window.

Now, supposing I were to go into ide-pmac and hard code an interrupt of 14
for the ohare bridge, rather than 13.  Are there other places in the code
that I need to worry about this (14 is a free irq according to
/proc/interrupts when I boot sans Sonnet card).

Thanks for taking the time to help figure out what's up with this.

Cheers,
Keith


On Sun, Jan 14, 2001 at 01:21:47PM +0100, Benjamin Herrenschmidt wrote:
> >Also, while this is probably a BAD idea, is it possible to create a BootX
> >build
> >where the g_l2cr_available (i think that's right) flag is set to true
> from the
> >start so that the Set G3 cache option is available for me?  Using the
> >powerlogix util I can find the G3 Cache value and I can use resedit to set it
> >by hand in the BootX Settings file. Then maybe have a bunch of debugging
> >output or something.
> >
> >I don't expect this to be a magic bullet or anything but I'm hoping to
> >understand where things are going wrong and see if it can be worked around.
> >
> >Sorry to bug you Ben . . if I had CodeWarrior myself, I'd be able to do more
> >experimentation myself first.
> 
> The hda: lost interrupt problems and the G3/L2 cache issues are 2
> different things.
> 
> Is your Sonet card also providing an IDE interface ? In this case, it's
> possible that the chipset on this card is not supported by 2.2.18 without
> the big IDE patch (which need to be fixed for powerpc).
> 
> For the G3, I'd rather figure out the correct L2CR value and "fix" it
> from userland (via /proc)
> 
> Ben.

-- 
<><><><><><><><><><><><>
Keith Clayton
clay-ton@pacbell.net

"If you don't trust me with your source code,
            why should I trust you with my computer?"

GPG key: http://home.pacbell.net/clay-ton/keith_public_key.html         
         http://www.keyserver.net                             
 
GPG fingerprint: 0C47 F1A1 0434 588C 9457  D53F D86A 5449 43F6 09A0  



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