From: David Edelsohn <dje@watson.ibm.com>
To: Dan Malek <dan@mvista.com>
Cc: Ralph Blach <rcblach@raleigh.ibm.com>,
frowand@mvista.com,
linuxppc-dev <linuxppc-dev@lists.linuxppc.org>
Subject: Re: kernel mapping
Date: Tue, 16 Jan 2001 12:47:16 -0500 [thread overview]
Message-ID: <200101161747.MAA22402@mal-ach.watson.ibm.com> (raw)
In-Reply-To: Message from Dan Malek <dan@mvista.com> of "Tue, 16 Jan 2001 11:50:15 EST." <3A647BC7.15F669F3@mvista.com>
>>>>> Dan Malek writes:
Dan> I have been experimenting with many different methods of using
Dan> the "large" page table sizes through the generic memory management
Dan> methods that already exist in the kernel. I believe I can wrap
Dan> the concept of the pinned TLB entries into the same logic as BAT
Dan> register management on the bigger processors. Hence, I call them
Dan> simulated BAT registers....the semantics aren't quite the same.
Note that forthcoming 64-bit PowerPC chips from IBM utilize
multiple page sizes and no longer provide BAT registers. "BAT register
management on the bigger processors" is a misnomer.
David
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
next prev parent reply other threads:[~2001-01-16 17:47 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-01-15 23:13 kernel mapping Dan Malek
2001-01-16 3:07 ` Frank Rowand
2001-01-16 3:55 ` Dan Malek
2001-01-16 11:37 ` Ralph Blach
2001-01-16 16:50 ` Dan Malek
2001-01-16 17:10 ` Ralph Blach
2001-01-16 17:47 ` David Edelsohn [this message]
2001-01-16 21:57 ` Dan Malek
2001-01-17 10:51 ` Gabriel Paubert
2001-01-17 17:45 ` David Edelsohn
2001-01-16 19:56 ` Frank Rowand
2001-01-16 22:13 ` Dan Malek
2001-01-17 0:04 ` Frank Rowand
2001-01-17 7:02 ` Dan Malek
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