From: Samuel Rydh <samuel@ibrium.se>
To: linuxppc-dev@lists.linuxppc.org
Subject: I-cache flushing on the 7400
Date: Sat, 31 Mar 2001 15:30:31 +0200 [thread overview]
Message-ID: <20010331153031.A10946@ibrium.se> (raw)
I recently discovered that the following sequence
LI_PHYS( r2,split_store_patch )
stw r4,0(r2) // store instruction
dcbst 0,r2 // Flush cache
sync
icbi 0,r2
isync
.... some instructions and then a rfi to split_store_patch ....
rfi
split_store_patch:
nop
did not work properly on a G4s (but it did work flawlessly on my G3).
To make the i-cache flush effective, I had to insert an extra
'sync' before the last isync. Consulting my Motorola manuals,
the recommended sequence for the 7400 (but not for the 750) did have
that extra sync. Looking at the 2.4.3-pre8 BK source, I discovered
the 'sync' was sometimes missing (in flush_icache_range and in a
few places in head.S). Shouldn't the sync really be added?
/Samuel
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next reply other threads:[~2001-03-31 13:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-03-31 13:30 Samuel Rydh [this message]
2001-03-31 17:07 ` I-cache flushing on the 7400 Benjamin Herrenschmidt
2001-03-31 17:51 ` Gabriel Paubert
2001-03-31 18:15 ` Samuel Rydh
2001-03-31 19:26 ` Gabriel Paubert
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