mvme5100 one more time...

mvme5100 one more time...

[Xavier Grave]

Hi,

I have compiled the last 2.4.10-pre1 kernel from linuxppc_2_4_devel
and I try to do a :
ppc6bug> nbo 0 0 ,,, zImage.pplus

The only thing I have is the following :
Exception : Program (Illegal instruction)
.... ....

Can somebody send me his .config file ?

Thanks in advance, xavier
--
33 (0) 1 69 15 79 59
De chacun selon ses forces, a chacun selon ses besoins

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Tom Rini]

On Thu, Aug 30, 2001 at 05:00:43PM +0200, Xavier Grave wrote:

> I have compiled the last 2.4.10-pre1 kernel from linuxppc_2_4_devel
> and I try to do a :
> ppc6bug> nbo 0 0 ,,, zImage.pplus
>
> The only thing I have is the following :
> Exception : Program (Illegal instruction)

What CPU is this?  I'm assuming you get a register dump, can you post that
too?

--
Tom Rini (TR1265)
http://gate.crashing.org/~trini/

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Xavier Grave]

Le jeu, 30 aoû 2001 18:19:36, Tom Rini a écrit :
>
> On Thu, Aug 30, 2001 at 05:00:43PM +0200, Xavier Grave wrote:
>
> > I have compiled the last 2.4.10-pre1 kernel from linuxppc_2_4_devel
> > and I try to do a :
> > ppc6bug> nbo 0 0 ,,, zImage.pplus
> >
> > The only thing I have is the following :
> > Exception : Program (Illegal instruction)

> What CPU is this?  I'm assuming you get a register dump, can you post
> that
> too?

I recompiled a kernel with the mvme5100_defconfig, the only difference is
that  CONFIG_PPC_STD_MMU=y is set

The error is the following :
Loading: zImage.pplus

Client IP Address      = 192.168.120.38
Server IP Address      = 192.168.120.35
Gateway IP Address     = 0.0.0.0
Subnet IP Address Mask = 255.255.255.0
Boot File Name         = zImage.pplus
Argument File Name     =

Network Boot File load in progress... To abort hit <BREAK>

Bytes Received =&701581, Bytes Loaded =&701581
Bytes/Second   =&701581, Elapsed Time =1 Second(s)

Exception: Program (Illegal Instruction)
SRR0 =001F0000 SRR1 =00083040 Vector-Offset =00700
IP     =001F0000 MSR    =00003040 CR     =00000000 FPSCR  =00000000
R0     =00000000 R1     =03F00000 R2     =00000000 R3     =00000000
R4     =00000000 R5     =49504C01 R6     =00007000 R7     =001F0000
R8     =03F0CF54 R9     =03F0CD54 R10    =03F0CD60 R11    =03F0CE54
R12    =03F0CE54 R13    =00000000 R14    =00000000 R15    =00000000
R16    =00000000 R17    =00000000 R18    =00000000 R19    =00000000
R20    =00000000 R21    =00000000 R22    =00000000 R23    =00000000
R24    =00000000 R25    =00000000 R26    =00000000 R27    =00000000
R28    =00000000 R29    =00000000 R30    =00000000 R31    =00000000
SPR0   =00000000 SPR1   =00000000 SPR8   =00000000 SPR9   =00000000
001F0000 00040000  WORD        $00040000

I will have a new try without the MMU CONFIG set...

xavier
--
33 (0) 1 69 15 79 59
De chacun selon ses forces, a chacun selon ses besoins

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Xavier Grave]

>
> What CPU is this?  I'm assuming you get a register dump, can you post
> that
> too?

Sorry I forgot the CPU information : G4 at 400 Mhz (I hope so, I will try a
compilation without altivec)
--
33 (0) 1 69 15 79 59
De chacun selon ses forces, a chacun selon ses besoins

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Tom Rini]

On Fri, Aug 31, 2001 at 11:16:29AM +0200, Xavier Grave wrote:
>
> Le jeu, 30 ao? 2001 18:19:36, Tom Rini a ?crit :
> >
> > On Thu, Aug 30, 2001 at 05:00:43PM +0200, Xavier Grave wrote:
> >
> > > I have compiled the last 2.4.10-pre1 kernel from linuxppc_2_4_devel
> > > and I try to do a :
> > > ppc6bug> nbo 0 0 ,,, zImage.pplus
> > >
> > > The only thing I have is the following :
> > > Exception : Program (Illegal instruction)
>
> > What CPU is this?  I'm assuming you get a register dump, can you post
> > that
> > too?
>
> I recompiled a kernel with the mvme5100_defconfig, the only difference is
> that  CONFIG_PPC_STD_MMU=y is set

That's fine..  Can you change arch/ppc/boot/simple/head.S to something like:
#if 0
/*
 * Determine CPU type
...
	bge	_setup_L2CR
#endif
	b	_setup_6xx

If this works, cat /proc/cpuinfo and tell me the PVR of your G4.

--
Tom Rini (TR1265)
http://gate.crashing.org/~trini/

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Xavier Grave]

[-- Attachment #1: Type: text/plain, Size: 1812 bytes --]


> That's fine..  Can you change arch/ppc/boot/simple/head.S to something
> like:
> #if 0
> /*
>  * Determine CPU type
> ...
> 	bge	_setup_L2CR
> #endif
> 	b	_setup_6xx
Thanks for your advice.

I do on my x86 cpu :
make CROSS_COMPILE=powerpc-unknown-linux-gnu- ARCH=ppc znetboot
on my 5100 :
PPC6-Bug>nbo 0 0 ,,, zImage.pplus
Network Booting from: I82559, Controller 0, Device 0
Device Name: /pci@fe000000/pci8086,1209@e,0:0,0
Loading: zImage.pplus

Client IP Address      = 192.168.120.38
Server IP Address      = 192.168.120.35
Gateway IP Address     = 0.0.0.0
Subnet IP Address Mask = 255.255.255.0
Boot File Name         = zImage.pplus
Argument File Name     =

Network Boot File load in progress... To abort hit <BREAK>

Bytes Received =&700757, Bytes Loaded =&700757
Bytes/Second   =&700757, Elapsed Time =1 Second(s)

Exception: Program (Illegal Instruction)
SRR0 =001F0000 SRR1 =00083040 Vector-Offset =00700
IP     =001F0000 MSR    =00003040 CR     =00000000 FPSCR  =00000000
R0     =00000000 R1     =03F00000 R2     =00000000 R3     =00000000
R4     =00000000 R5     =49504C01 R6     =00007000 R7     =001F0000
R8     =03F0CF54 R9     =03F0CD54 R10    =03F0CD60 R11    =03F0CE54
R12    =03F0CE54 R13    =00000000 R14    =00000000 R15    =00000000
R16    =00000000 R17    =00000000 R18    =00000000 R19    =00000000
R20    =00000000 R21    =00000000 R22    =00000000 R23    =00000000
R24    =00000000 R25    =00000000 R26    =00000000 R27    =00000000
R28    =00000000 R29    =00000000 R30    =00000000 R31    =00000000
SPR0   =00000000 SPR1   =00000000 SPR8   =00000000 SPR9   =00000000
001F0000 00040000  WORD        $00040000

I have done the modification you advised me and also an other one (to
compile :-(

Any idea ?
--
33 (0) 1 69 15 79 59
De chacun selon ses forces, a chacun selon ses besoins

[-- Attachment #2: head.S --]
[-- Type: application/octet-stream, Size: 8243 bytes --]

/*
 * arch/ppc/boot/simple/head.S
 * 
 * Initial board bringup code for many different boards.
 *
 * Author: Tom Rini
 *	   trini@mvista.com
 * Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others).
 *
 * Copyright 2001 MontaVista Software Inc.
 *
 * Part of the philosphy behind this is to keep #ifdefs to a minimum.
 * However, this doesn't always works.  For example, the Force PowerCore
 * machines _need_ to have the L1 disabled early on or they won't get to
 * the spot everyone else with that CPU gets it.  And for _setup_embed,
 * it would be more complex than needed to return early on !8xx.
 *
 * Having said that, it's still not a good excuse to add in more, unless it's
 * very neccessary.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/config.h>
#include "../../kernel/ppc_defs.h"
#include "../../kernel/ppc_asm.tmpl"
#include <asm/processor.h>
#include <asm/cache.h>

/* List of PVR masks.
 * Here's how the magic works.  First we look for 4xx.  No BATs, no
 * mucking with L1/L2, just get things going.  Then we look for 8xx,
 * and do any magic needed there.  If we get beyond these masks,
 * we assume a CPU which we can enable/invalidate/disable the L1 on.
 * Then later on, we will clear the BATs and setup segment registers.
 * The next set of masks we check for is to see if we can talk to the
 * L2CR.  If we can, we will invalidate/disable and re-enable the L2,
 * to work around possibly buggy firmware implementations. -- Tom
 */

#define	IBM403	0x00000200	/* IBM 403 series */
#define	IBM405	0x00004000	/* IBM 405 series */
#define	MPC8XX	0x00000050	/* Motorola MPC8xx */
#define	PPC750	0x00000008	/* PowerPC 740/750 */
#define	PPC7400	0x0000000C	/* PowerPC 7400 */
#define	PPC7410	0x0000800C	/* PowerPC 7410 */

	.text

/* This macro is used to test the PVR of the current CPU to a given one,
 * PROC.
 */
#define	TEST(PROC)							\
	lis	r9,PROC@h;	/* Load the mask into r9 */		\
	ori	r9,r9,PROC@l;						\
	and	r6,r7,r9;	/* r6 = PVR & mask */			\
	cmplw	r9,r6;		/* compare the mask to the original */	\
	beq	test;		/* If equal, test which kind we have */	\
	addi	r8,r8,1;	/* count++ */

/*
 *      Begin at some arbitrary location in RAM or Flash
 *        Test PVR to determine CPU type, act occordingly.
 *	  Initialize core registers
 *	  Configure memory controller (Not executing from RAM)
 *	Move the boot code to the link address (8M)
 *	  Setup C stack
 *	  Initialize UART
 *      Decompress the kernel to 0x0
 *      Jump to the kernel entry
 *
 */

	.globl	start
start:
	bl	start_
	/* The IBM "Tree" bootrom knows that the address of the bootrom
	 * read only structure is 4 bytes after _start.
	 */
	.long	0x62726f6d		# structure ID - "brom"
	.long	0x5f726f00		#              - "_ro\0"
	.long	1			# structure version

start_:
#ifdef CONFIG_PCORE
	/* We have some really bad firmware.  We must disable the L1 
	 * icache/dcache now or the board won't boot.
	 */
	li	r4,0x0000
	isync
	mtspr	HID0,r4
	sync
	isync
#endif

	mr	r25,r3		/* Possibly save something. */
/*
 * Determine what CPU we're on.
 */
	lis	r8,0		/* count == 0 */
	mfpvr	r7		/* Get the PVR */
	srawi	r7,r7,16	/* Just the first 16 bits */
	TEST(IBM403)		/* Check for a 403 */
	TEST(IBM405)		/* Check for a 405 */
	TEST(MPC8XX)		/* Check for an MPC8xx */
	TEST(PPC750)		/* Check for a 740 or 750 */
	TEST(PPC7400)		/* Check for a 7400 */
	TEST(PPC7410)		/* Check for a 7410 */
test:
	/* What might be nice is testing for 4xx/8xx, and if we aren't
	 * on either of those, setup the default MSR, and test more.
	 * Or we could even test for r8 == 6 later on.
	 */
	b	_setup_6xx
#if 0
	cmplwi	r8,0x0002	/* Test if we're <= 2, if so we're 8xx, */
	ble	_setup_embed	/* or 4xx. */
	cmplwi	r8,0x0006	/* Test if we're == 6, if so, do generic 6xx */
	beq	_setup_6xx	/* early setup. */
	cmplwi	r8,0x0003	/* Test if we're >= 3, if so assume we */
	bge	_setup_L2CR	/* should reset the L2CR */
#endif
/* Come back to here, once we've done our early init stuffs. */
doneEarly:
	/* compute the size of the whole image in words. */
	lis	r4,start@h
	ori	r4,r4,start@l
	lis	r5,end@h
	ori	r5,r5,end@l
	addi	r5,r5,3		/* round up */
	sub	r5,r5,r4	/* end - start */
	srwi	r5,r5,2
	mr	r7,r5		/* Save for later use. */

	/* check if we need to relocate ourselves to the link addr or were 
	 * we loaded there to begin with -- Cort */
	mflr	r3
	subi	r3,r3,4		/* we get the nip, not the ip of the branch */
	mr	r8,r3
	cmp	cr0,r3,r4
	beq	start_ldr	/* If 0, we don't need to relocate */

	/* 
	 * no matter where we're loaded, move ourselves to -Ttext address
	 */
	mflr	r3		/* Compute code bias */
	subi	r3,r3,4
	mr	r8,r3
	lis	r4,start@h
	ori	r4,r4,start@l
	mr	r5,r7		/* Get the # of longwords again */
	mtctr	r5		/* Setup for a loop */
	li	r6,0
	subi	r3,r3,4
	subi	r4,r4,4
00:	lwzu	r5,4(r3)
	stwu	r5,4(r4)
	xor	r6,r6,r5
	bdnz	00b
	lis	r3,start_ldr@h
	ori	r3,r3,start_ldr@l
	mtlr	r3		/* Easiest way to do an absolute jump */
	blr

start_ldr:
/* Some boards don't boot up with the I-cache enabled.  Do that
 * now because the decompress runs much faster that way.
 * As a side effect, we have to ensure the data cache is not enabled
 * so we can access the serial I/O without trouble.
 */
	bl	flush_instruction_cache

	/* Clear all of BSS and set up stack for C calls */
	lis	r3,edata@h
	ori	r3,r3,edata@l
	lis	r4,end@h
	ori	r4,r4,end@l
	subi	r3,r3,4
	subi	r4,r4,4
	li	r0,0
50:	stwu	r0,4(r3)
	cmp	cr0,r3,r4
	bne	50b
90:	mr	r9,r1		/* Save old stack pointer (in case it matters) */
	lis	r1,.stack@h
	ori	r1,r1,.stack@l
	addi	r1,r1,4096*2
	subi	r1,r1,256
	li	r2,0x000F	/* Mask pointer to 16-byte boundary */
	andc	r1,r1,r2

	/*
	 * Exec kernel loader
	 */
	mr	r3,r8		/* Load point */
	mr	r4,r7		/* Program length */
	mr	r5,r6		/* Checksum */
	mr	r6,r11		/* Residual data */
	bl	decompress_kernel
	
	lis	r6,cmd_line@h
	ori	r6,r6,cmd_line@l
	lwz	r6,0(r6)
	subi	r7,r6,1
00:	lbzu	r2,1(r7)
	cmpi	cr0,r2,0
	bne	00b

	/* r4,r5 have initrd_start, size */
	lis	r2,initrd_start@h
	ori	r2,r2,initrd_start@l
	lwz	r4,0(r2)
	lis	r2,initrd_end@h
	ori	r2,r2,initrd_end@l
	lwz	r5,0(r2)

	/*
	 * Start at the begining.
	 */
	li	r9,0x0000
	mtlr	r9
	blr

/* Setup various CPU types. */

_setup_L2CR:
/*
 * We should be skipping this section on CPUs where this results in an
 * illegal instruction.  If not, please send trini@kernel.crashing.org
 * the PVR of your CPU.
 */
	/* Invalidate/disable L2 cache */
	mfspr	r4,L2CR
	andis.	r4,r4,0x7fff
	oris	r4,r4,0x0020
	isync
	mtspr	L2CR,r4
	sync
	isync

	/* Reenable L2 cache */
	mfspr	r4,L2CR
	oris	r4,r4,0x8000
	isync
	mtspr	L2CR,r4
	sync
	isync
_setup_6xx:
/*
 * Configure core registers
 */
	/* Establish default MSR value, exception prefix 0xFFF */
	li	r3,MSR_IP|MSR_FP
	mtmsr	r3

	/* Clear BATs */
	li	r8,0
	mtspr	DBAT0U,r8
	mtspr	DBAT0L,r8
	mtspr	DBAT1U,r8
	mtspr	DBAT1L,r8
	mtspr	DBAT2U,r8
	mtspr	DBAT2L,r8
	mtspr	DBAT3U,r8
	mtspr	DBAT3L,r8
	mtspr	IBAT0U,r8
	mtspr	IBAT0L,r8
	mtspr	IBAT1U,r8
	mtspr	IBAT1L,r8
	mtspr	IBAT2U,r8
	mtspr	IBAT2L,r8
	mtspr	IBAT3U,r8
	mtspr	IBAT3L,r8
	isync
	sync
	sync

	/* Set segment registers */
	lis	r8,0x8000
	isync
	mtsr	SR0,r8
	mtsr	SR1,r8
	mtsr	SR2,r8
	mtsr	SR3,r8
	mtsr	SR4,r8
	mtsr	SR5,r8
	mtsr	SR6,r8
	mtsr	SR7,r8
	mtsr	SR8,r8
	mtsr	SR9,r8
	mtsr	SR10,r8
	mtsr	SR11,r8
	mtsr	SR12,r8
	mtsr	SR13,r8
	mtsr	SR14,r8
	mtsr	SR15,r8
	isync
	sync
	sync

	/* Enable, invalidate and then disable the L1 icache/dcache. */
	li	r8,0
	ori	r8,r8,(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
	mfspr	r11,HID0
	or	r11,r11,r8
	andc	r10,r11,r8
	isync
	mtspr	HID0,r8
	sync
	isync
	mtspr	HID0,r10
	sync
	isync

	b	doneEarly	/* Done with early init stuffs */

/* MPC8xx CPUs */
_setup_embed:
	mfmsr	r3		/* Turn off interrupts */
	li	r4,0
	ori	r4,r4,MSR_EE
	andc	r3,r3,r4
	mtmsr	r3

#ifdef CONFIG_8xx
	/* We do this because some boot roms don't initialize the
	 * processor correctly. Don't do this if you want to debug
	 * using a BDM device.
	 */
	li	r4,0		/* Zero DER to prevent FRZ */
	mtspr	SPRN_DER,r4
#endif

	b	doneEarly	/* Done with early init stuffs */

	.comm	.stack,4096*2,4

Re: mvme5100 one more time...

[Tom Rini]

On Fri, Aug 31, 2001 at 05:36:34PM +0200, Xavier Grave wrote:
>
> > That's fine..  Can you change arch/ppc/boot/simple/head.S to something
> > like:
> > #if 0
> > /*
> >  * Determine CPU type
> > ...
> > 	bge	_setup_L2CR
> > #endif
> > 	b	_setup_6xx
> Thanks for your advice.
>
> I do on my x86 cpu :
> make CROSS_COMPILE=powerpc-unknown-linux-gnu- ARCH=ppc znetboot
> on my 5100 :
> PPC6-Bug>nbo 0 0 ,,, zImage.pplus
> Network Booting from: I82559, Controller 0, Device 0
> Device Name: /pci@fe000000/pci8086,1209@e,0:0,0
> Loading: zImage.pplus
>
> Client IP Address      = 192.168.120.38
> Server IP Address      = 192.168.120.35
> Gateway IP Address     = 0.0.0.0
> Subnet IP Address Mask = 255.255.255.0
> Boot File Name         = zImage.pplus
> Argument File Name     =
>
> Network Boot File load in progress... To abort hit <BREAK>
>
> Bytes Received =&700757, Bytes Loaded =&700757
> Bytes/Second   =&700757, Elapsed Time =1 Second(s)
>
> Exception: Program (Illegal Instruction)
> SRR0 =001F0000 SRR1 =00083040 Vector-Offset =00700
> IP     =001F0000 MSR    =00003040 CR     =00000000 FPSCR  =00000000
> R0     =00000000 R1     =03F00000 R2     =00000000 R3     =00000000
> R4     =00000000 R5     =49504C01 R6     =00007000 R7     =001F0000
> R8     =03F0CF54 R9     =03F0CD54 R10    =03F0CD60 R11    =03F0CE54
> R12    =03F0CE54 R13    =00000000 R14    =00000000 R15    =00000000
> R16    =00000000 R17    =00000000 R18    =00000000 R19    =00000000
> R20    =00000000 R21    =00000000 R22    =00000000 R23    =00000000
> R24    =00000000 R25    =00000000 R26    =00000000 R27    =00000000
> R28    =00000000 R29    =00000000 R30    =00000000 R31    =00000000
> SPR0   =00000000 SPR1   =00000000 SPR8   =00000000 SPR9   =00000000
> 001F0000 00040000  WORD        $00040000
>
> I have done the modification you advised me and also an other one (to
> compile :-(

Okay.  Try this.  Undo what I told you last time, and make the end of
the file look like:
#if 0

	.comm	.stack,4096*2,4
#endif

This may or may not compile.  I have a feeling there'll be some egg on
my face shortly...

--
Tom Rini (TR1265)
http://gate.crashing.org/~trini/

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Xavier Grave]

Le ven, 31 aoû 2001 17:49:27, Tom Rini a écrit :
>
> On Fri, Aug 31, 2001 at 05:36:34PM +0200, Xavier Grave wrote:
> >
> > > That's fine..  Can you change arch/ppc/boot/simple/head.S to
> something
> > > like:
> > > #if 0
> > > /*
> > >  * Determine CPU type
> > > ...
> > > 	bge	_setup_L2CR
> > > #endif
> > > 	b	_setup_6xx
> > Thanks for your advice.
> >
> > I do on my x86 cpu :
> > make CROSS_COMPILE=powerpc-unknown-linux-gnu- ARCH=ppc znetboot
> > on my 5100 :
> > PPC6-Bug>nbo 0 0 ,,, zImage.pplus
> > Network Booting from: I82559, Controller 0, Device 0
> > Device Name: /pci@fe000000/pci8086,1209@e,0:0,0
> > Loading: zImage.pplus
> >
> > Client IP Address      = 192.168.120.38
> > Server IP Address      = 192.168.120.35
> > Gateway IP Address     = 0.0.0.0
> > Subnet IP Address Mask = 255.255.255.0
> > Boot File Name         = zImage.pplus
> > Argument File Name     =
> >
> > Network Boot File load in progress... To abort hit <BREAK>
> >
> > Bytes Received =&700757, Bytes Loaded =&700757
> > Bytes/Second   =&700757, Elapsed Time =1 Second(s)
> >
> > Exception: Program (Illegal Instruction)
> > SRR0 =001F0000 SRR1 =00083040 Vector-Offset =00700
> > IP     =001F0000 MSR    =00003040 CR     =00000000 FPSCR  =00000000
> > R0     =00000000 R1     =03F00000 R2     =00000000 R3     =00000000
> > R4     =00000000 R5     =49504C01 R6     =00007000 R7     =001F0000
> > R8     =03F0CF54 R9     =03F0CD54 R10    =03F0CD60 R11    =03F0CE54
> > R12    =03F0CE54 R13    =00000000 R14    =00000000 R15    =00000000
> > R16    =00000000 R17    =00000000 R18    =00000000 R19    =00000000
> > R20    =00000000 R21    =00000000 R22    =00000000 R23    =00000000
> > R24    =00000000 R25    =00000000 R26    =00000000 R27    =00000000
> > R28    =00000000 R29    =00000000 R30    =00000000 R31    =00000000
> > SPR0   =00000000 SPR1   =00000000 SPR8   =00000000 SPR9   =00000000
> > 001F0000 00040000  WORD        $00040000
> >
> > I have done the modification you advised me and also an other one (to
> > compile :-(
>
> Okay.  Try this.  Undo what I told you last time, and make the end of
> the file look like:
> #if 0
>
> 	.comm	.stack,4096*2,4
> #endif
>
> This may or may not compile.  I have a feeling there'll be some egg on
> my face shortly...

it doesn't compile : I have the following message :
head.o: In function `start_ldr':
head.o(.text+0x176): undefined reference to `stack'
head.o(.text+0x17a): undefined reference to `stack'
make[2]: *** [zvmlinux] Erreur 1

Why the eggs ? because it doesn't compile ? :-)

--
33 (0) 1 69 15 79 59
De chacun selon ses forces, a chacun selon ses besoins

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Tom Rini]

On Fri, Aug 31, 2001 at 06:03:36PM +0200, Xavier Grave wrote:
>
> Le ven, 31 ao? 2001 17:49:27, Tom Rini a ?crit :
> >
> > Okay.  Try this.  Undo what I told you last time, and make the end of
> > the file look like:
> > #if 0
> >
> > 	.comm	.stack,4096*2,4
> > #endif
> >
> > This may or may not compile.  I have a feeling there'll be some egg on
> > my face shortly...
>
> it doesn't compile : I have the following message :
> head.o: In function `start_ldr':
> head.o(.text+0x176): undefined reference to `stack'
> head.o(.text+0x17a): undefined reference to `stack'
> make[2]: *** [zvmlinux] Erreur 1
>
> Why the eggs ? because it doesn't compile ? :-)

Well, my guess is that .stack is being defined twice, maybe...  The reg dump
makes it look like it's about to goto decompress_kernel.  Can you try the
following patch?  And undo what Itold you to do last time..

--
Tom Rini (TR1265)
http://gate.crashing.org/~trini/

===== arch/ppc/boot/common/util.S 1.1 vs edited =====
--- 1.1/arch/ppc/boot/common/util.S	Thu Aug  2 16:02:25 2001
+++ edited/arch/ppc/boot/common/util.S	Fri Aug 31 09:01:10 2001
@@ -116,4 +116,3 @@
 	addi	r3,r3,CACHE_LINE_SIZE	/* Next line, please */
 	bdnz	00b
 10:	blr
-	.comm	.stack,4096*2,4
===== arch/ppc/boot/prep/head.S 1.15 vs edited =====
--- 1.15/arch/ppc/boot/prep/head.S	Tue Aug 28 15:57:32 2001
+++ edited/arch/ppc/boot/prep/head.S	Fri Aug 31 09:00:56 2001
@@ -178,11 +178,9 @@
 	ori	r2,r2,initrd_end@l
 	lwz	r5,0(r2)

-
-	/* tell kernel we're prep */
-	/*
-	 * get start address of kernel code which is stored as a coff
-	 * entry.  see boot/head.S -- Cort
+	/* tell kernel we're prep, by putting 0xdeadc0de at KERNELLOAD,
+	 * and tell the kernel to start on the 4th instruction since we
+	 * overwrite the first 3 sometimes (which are 'nop').
 	 */
 	li	r9,0xc
 	mtlr	r9
@@ -191,5 +189,5 @@
 	li	r9,0
 	stw	r10,0(r9)
 	blr
-hang:
-	b	hang
+
+	.comm	.stack,4096*2,4

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Tom Rini]

On Fri, Aug 31, 2001 at 11:09:38AM -0700, Tom Rini wrote:
>
> On Fri, Aug 31, 2001 at 06:03:36PM +0200, Xavier Grave wrote:
> >
> > Le ven, 31 ao? 2001 17:49:27, Tom Rini a ?crit :
> > >
> > > Okay.  Try this.  Undo what I told you last time, and make the end of
> > > the file look like:
> > > #if 0
> > >
> > > 	.comm	.stack,4096*2,4
> > > #endif
> > >
> > > This may or may not compile.  I have a feeling there'll be some egg on
> > > my face shortly...
> >
> > it doesn't compile : I have the following message :
> > head.o: In function `start_ldr':
> > head.o(.text+0x176): undefined reference to `stack'
> > head.o(.text+0x17a): undefined reference to `stack'
> > make[2]: *** [zvmlinux] Erreur 1
> >
> > Why the eggs ? because it doesn't compile ? :-)
>
> Well, my guess is that .stack is being defined twice, maybe...  The reg dump
> makes it look like it's about to goto decompress_kernel.  Can you try the
> following patch?  And undo what Itold you to do last time..

And if this fails, I just thought of one more thing (I need some hw I can
test this on locally...).
Look for:
	bl	flush_instruction_cache
And add #if 0/#endif around that and try again...

--
Tom Rini (TR1265)
http://gate.crashing.org/~trini/

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Xavier Grave]

Le sam, 01 sep 2001 01:29:04, Tom Rini a écrit :

> And if this fails, I just thought of one more thing (I need some hw I can
> test this on locally...).
> Look for:
> 	bl	flush_instruction_cache
> And add #if 0/#endif around that and try again...

I have done a pull this morning and applied your patchs. I have the same
results even
after the bl	flush_instruction_cache suppression.

Here is the result :
Network Boot File load in progress... To abort hit <BREAK>

Bytes Received =&701661, Bytes Loaded =&701661
Bytes/Second   =&701661, Elapsed Time =1 Second(s)

Exception: Program (Illegal Instruction)
SRR0 =001F0000 SRR1 =00083040 Vector-Offset =00700
IP     =001F0000 MSR    =00003040 CR     =00000000 FPSCR  =00000000
R0     =00000000 R1     =03F00000 R2     =00000000 R3     =00000000
R4     =00000000 R5     =49504C01 R6     =00007000 R7     =001F0000
R8     =03F0CF54 R9     =03F0CD54 R10    =03F0CD60 R11    =03F0CE54
R12    =03F0CE54 R13    =00000000 R14    =00000000 R15    =00000000
R16    =00000000 R17    =00000000 R18    =00000000 R19    =00000000
R20    =00000000 R21    =00000000 R22    =00000000 R23    =00000000
R24    =00000000 R25    =00000000 R26    =00000000 R27    =00000000
R28    =00000000 R29    =00000000 R30    =00000000 R31    =00000000
SPR0   =00000000 SPR1   =00000000 SPR8   =00000000 SPR9   =00000000
001F0000 00040000  WORD        $00040000

The board don't have any disk or system for the moment, perhaps this is the
problem ?
I just want to try to boot now... Because I have also a mvme2303 with a
whole debian
system on it. So if I have a kernel for the mvme5100 I will only need to
put my
SCSI PMC to have a complete system.

O+ xavier

--
33 (0) 1 69 15 79 59
De chacun selon ses forces, a chacun selon ses besoins

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Lorenzo Pivetta]

Xavier Grave wrote:
> The board don't have any disk or system for the moment, perhaps this is the
> problem ?
> I just want to try to boot now... Because I have also a mvme2303 with a
> whole debian
> system on it. So if I have a kernel for the mvme5100 I will only need to
> put my
> SCSI PMC to have a complete system.

I got it running, either booting from the net or from hard disk, but
I'm using kernel version 2.4.7 from linuxppc_2_4_devel, downloaded
on 24 July. I'll try 2.4.10-pre4.

Lorenzo.

--
Ing. Lorenzo Pivetta       \ e-mail: lorenzo.pivetta@elettra.trieste.it
                            \ tel.:  040 - 3758361 - fax: 040 - 9380902
Sincrotrone Trieste S.C.p.A. \ url:  http://www.elettra.trieste.it

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Brian Waite]

Xavier,
	Just a quick sanity check, are all the jumpers at factory default and have
you changed any env settings? Just a thought.

Thanks
Brian

On Monday 03 September 2001 11:32 am, you wrote:
> Le sam, 01 sep 2001 01:29:04, Tom Rini a
> écrit :
> > And if this fails, I just thought of one more thing (I need some hw I can
> > test this on locally...).
> > Look for:
> >    bl   flush_instruction_cache
> > And add #if 0/#endif around that and try again...
>
> I have done a pull this morning and applied your patchs. I have the same
> results even
> after the bl   flush_instruction_cache suppression.
>
> Here is the result :
> Network Boot File load in progress... To abort hit <BREAK>
>
> Bytes Received =&701661, Bytes Loaded =&701661
> Bytes/Second   =&701661, Elapsed Time =1 Second(s)
>
> Exception: Program (Illegal Instruction)
> SRR0 =001F0000 SRR1 =00083040 Vector-Offset =00700
> IP     =001F0000 MSR    =00003040 CR     =00000000 FPSCR  =00000000
> R0     =00000000 R1     =03F00000 R2     =00000000 R3     =00000000
> R4     =00000000 R5     =49504C01 R6     =00007000 R7     =001F0000
> R8     =03F0CF54 R9     =03F0CD54 R10    =03F0CD60 R11    =03F0CE54
> R12    =03F0CE54 R13    =00000000 R14    =00000000 R15    =00000000
> R16    =00000000 R17    =00000000 R18    =00000000 R19    =00000000
> R20    =00000000 R21    =00000000 R22    =00000000 R23    =00000000
> R24    =00000000 R25    =00000000 R26    =00000000 R27    =00000000
> R28    =00000000 R29    =00000000 R30    =00000000 R31    =00000000
> SPR0   =00000000 SPR1   =00000000 SPR8   =00000000 SPR9   =00000000
> 001F0000 00040000  WORD        $00040000
>
> The board don't have any disk or system for the moment, perhaps this is the
> problem ?
> I just want to try to boot now... Because I have also a mvme2303 with a
> whole debian
> system on it. So if I have a kernel for the mvme5100 I will only need to
> put my
> SCSI PMC to have a complete system.
>
> O+ xavier

--
Brian Waite

Looking for a TeraFLOP in a closet
www.fastcluster.com

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Xavier Grave]

Le mar, 04 sep 2001 16:06:59, Brian Waite a écrit :
>
> Xavier,
> 	Just a quick sanity check, are all the jumpers at factory default
> and have
> you changed any env settings? Just a thought.
>
Hi Brian,

I don't have change any jumper or env variables.
Do I need to do so to boot with a tftp server ?

Thanks for your hint.

Xavier
--
33 (0) 1 69 15 79 59
De chacun selon ses forces, a chacun selon ses besoins

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Brian Waite]

Make sure you have set this env variable:
Network PReP-Boot Mode Enable [Y/N] = Y?


use env and  accept the defaults for everything else. Once you set Prep boot
mode to Y hit '.' to exit the env variable settings. Make sure you say 'Y'
when it asks you if you want to reset. Then try booting.


Thanks
Brian


On Tuesday 04 September 2001 10:28 am, you wrote:
> Le mar, 04 sep 2001 16:06:59, Brian Waite a
> écrit :
> > Xavier,
> >    Just a quick sanity check, are all the jumpers at factory default
> > and have
> > you changed any env settings? Just a thought.
>
> Hi Brian,
>
> I don't have change any jumper or env variables.
> Do I need to do so to boot with a tftp server ?
>
> Thanks for your hint.
>
> Xavier

--
Brian Waite

Looking for a TeraFLOP in a closet
www.fastcluster.com

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: mvme5100 one more time...

[Xavier Grave]

Shame on me !

I forgot to set the env variable...

After setting it my zImage.pplus give this result :
I have the usual linuxppc/load....

Thanks to every body for your help !

Xavier

Le mar, 04 sep 2001 16:56:07, Brian Waite a écrit :
>
> Make sure you have set this env variable:
> Network PReP-Boot Mode Enable [Y/N] = Y?
>
>
> use env and  accept the defaults for everything else. Once you set Prep
> boot
> mode to Y hit '.' to exit the env variable settings. Make sure you say
> 'Y'
> when it asks you if you want to reset. Then try booting.

--
33 (0) 1 69 15 79 59
De chacun selon ses forces, a chacun selon ses besoins

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/