[PATCH] New PHY for ppc405_phy.c

[PATCH] New PHY for ppc405_phy.c

[Kent Borg]

I hope I am sending this to the right place, someone please correct me
if I am doing this wrong...


Our 405 board has a different PHY from those supported in the current
sources, the following patch makes our PHY work.  If it looks
sensible, please apply.


Thanks,

-kb



--- linuxppc_2_4_devel/drivers/net/ppc405_phy.c	Thu Nov 29 10:34:53 2001
+++ linux-penguinppc4/drivers/net/ppc405_phy.c	Thu Nov 29 10:48:07 2001
@@ -579,6 +579,75 @@
 	},
 };

+/* ------------------------------------------------------------------------- */
+/* The Lucent Technologies LU3X31FT */
+
+/* register definitions */
+
+#define MII_LU3X31FT_PHYCTRLSTS 0x17    /* PHY Control/Status Register */
+#define MII_LU3X31FT_IER        0x1D    /* PHY interrupt enable Register */
+#define MII_LU3X31FT_ISR        0x1E    /* PHY interrupt status Register */
+
+static void mii_parse_lu3x31ft_pcr(uint mii_reg, struct net_device *dev)
+{
+	struct fec_enet_private *fep = dev->priv;
+	volatile uint *s = &(fep->phy_status);
+
+	*s &= ~(PHY_STAT_SPMASK);
+
+	switch((mii_reg >> 8) & 3) {
+		case 0:
+			*s |= PHY_STAT_10HDX;
+			break;
+		case 1:
+			*s |= PHY_STAT_10FDX;
+			break;
+		case 2:
+			*s |= PHY_STAT_100HDX;
+			break;
+		case 3:
+			*s |= PHY_STAT_100FDX;
+			break;
+	}
+}
+
+static phy_info_t phy_info_lu3x31ft = {
+	0x90307421,
+	"LU3X31FT",
+	0,
+	(const phy_cmd_t []) {	/* config */
+
+		/* parse cr and anar to get some info */
+
+		{ mk_mii_read(MII_REG_CR), mii_parse_cr },
+		{ mk_mii_read(MII_REG_ANAR), mii_parse_anar },
+		{ mk_mii_end, }
+	},
+	(const phy_cmd_t []) {	/* startup - enable interrupts */
+		{ mk_mii_write(MII_LU3X31FT_IER, 0x0000), NULL },
+		{ mk_mii_write(MII_REG_CR, PHY_BMCR_RST_NEG), NULL }, /* autonegotiate */
+		{ mk_mii_end, }
+	},
+	( const phy_cmd_t []) { /* ack_int */
+
+		/* we need to read ISR, SR and ANER to acknowledge */
+
+		{ mk_mii_read(MII_LU3X31FT_ISR), NULL },
+		{ mk_mii_read(MII_REG_SR), mii_parse_sr },
+		{ mk_mii_read(MII_REG_ANAR), mii_parse_anar },
+
+		/* read pcr to get info */
+
+		{ mk_mii_read(MII_LU3X31FT_PHYCTRLSTS), mii_parse_lu3x31ft_pcr },
+		{ mk_mii_end, }
+	},
+	( const phy_cmd_t []) {	/* shutdown - disable interrupts */
+		{ mk_mii_write(MII_LU3X31FT_IER, 0xff80), NULL },
+		{ mk_mii_end, }
+	},
+};
+
+

 /* ------------------------------------------------------------------------- */
 /* The AMD Am79C875*/
@@ -659,6 +728,7 @@
 	&phy_info_lxt971a,
 	&phy_info_cs8952,
 	&phy_info_dp83846A,
+	&phy_info_lu3x31ft,
 	&phy_info_Am79C875,
 	NULL
 };

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Re: [PATCH] New PHY for ppc405_phy.c

[Tom Rini]

On Thu, Nov 29, 2001 at 11:05:30AM -0500, Kent Borg wrote:

> I hope I am sending this to the right place, someone please correct me
> if I am doing this wrong...

Looks good, applied.

--
Tom Rini (TR1265)
http://gate.crashing.org/~trini/

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: [PATCH] New PHY for ppc405_phy.c

[Armin Kuster]

Kent Borg wrote:
>
> I hope I am sending this to the right place, someone please correct me
> if I am doing this wrong...
>
> Our 405 board has a different PHY from those supported in the current
> sources, the following patch makes our PHY work.  If it looks
> sensible, please apply.
>
> Thanks,
>
> -kb
>
> --- linuxppc_2_4_devel/drivers/net/ppc405_phy.c Thu Nov 29 10:34:53 2001
> +++ linux-penguinppc4/drivers/net/ppc405_phy.c  Thu Nov 29 10:48:07 2001
> @@ -579,6 +579,75 @@
>         },
>  };
>
> +/* ------------------------------------------------------------------------- */
> +/* The Lucent Technologies LU3X31FT */
> +
> +/* register definitions */
> +
> +#define MII_LU3X31FT_PHYCTRLSTS 0x17    /* PHY Control/Status Register */
> +#define MII_LU3X31FT_IER        0x1D    /* PHY interrupt enable Register */
> +#define MII_LU3X31FT_ISR        0x1E    /* PHY interrupt status Register */
> +
> +static void mii_parse_lu3x31ft_pcr(uint mii_reg, struct net_device *dev)
> +{
> +       struct fec_enet_private *fep = dev->priv;
> +       volatile uint *s = &(fep->phy_status);
> +
> +       *s &= ~(PHY_STAT_SPMASK);
> +
> +       switch((mii_reg >> 8) & 3) {
> +               case 0:
> +                       *s |= PHY_STAT_10HDX;
> +                       break;
> +               case 1:
> +                       *s |= PHY_STAT_10FDX;
> +                       break;
> +               case 2:
> +                       *s |= PHY_STAT_100HDX;
> +                       break;
> +               case 3:
> +                       *s |= PHY_STAT_100FDX;
> +                       break;
> +       }
> +}
> +
> +static phy_info_t phy_info_lu3x31ft = {
> +       0x90307421,
> +       "LU3X31FT",
> +       0,
> +       (const phy_cmd_t []) {  /* config */
> +
> +               /* parse cr and anar to get some info */
> +
> +               { mk_mii_read(MII_REG_CR), mii_parse_cr },
> +               { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
> +               { mk_mii_end, }
> +       },
> +       (const phy_cmd_t []) {  /* startup - enable interrupts */
> +               { mk_mii_write(MII_LU3X31FT_IER, 0x0000), NULL },
> +               { mk_mii_write(MII_REG_CR, PHY_BMCR_RST_NEG), NULL }, /* autonegotiate */
> +               { mk_mii_end, }
> +       },
> +       ( const phy_cmd_t []) { /* ack_int */
> +
> +               /* we need to read ISR, SR and ANER to acknowledge */
> +
> +               { mk_mii_read(MII_LU3X31FT_ISR), NULL },
> +               { mk_mii_read(MII_REG_SR), mii_parse_sr },
> +               { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
> +
> +               /* read pcr to get info */
> +
> +               { mk_mii_read(MII_LU3X31FT_PHYCTRLSTS), mii_parse_lu3x31ft_pcr },
> +               { mk_mii_end, }
> +       },
> +       ( const phy_cmd_t []) { /* shutdown - disable interrupts */
> +               { mk_mii_write(MII_LU3X31FT_IER, 0xff80), NULL },
> +               { mk_mii_end, }
> +       },
> +};
> +
> +
>
>  /* ------------------------------------------------------------------------- */
>  /* The AMD Am79C875*/
> @@ -659,6 +728,7 @@
>         &phy_info_lxt971a,
>         &phy_info_cs8952,
>         &phy_info_dp83846A,
> +       &phy_info_lu3x31ft,
>         &phy_info_Am79C875,
>         NULL
>  };
>


Thanks,

-- armin

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Debugging message through FDC37C672-COM of MBX860??

[Okehee Goh]

Hello,
I'm so sorry about this question.

I want to print out debug messages to console monitor from the
application loaded at MBX860 through EPPC-Bug. I was supposed to use
EPPC-Bug's system call for this purpose. But it wasn't possible because my
application overlap
all exception codes and stack. And then I tried to use SMC1 or SMC2's UART
for this purpose. But it's not working.

The port status is the following.
------------------
EPPC-Bug>pf
Current Port Assignments:  (LUN: Device-Name Port-Name)

00: FDC37C672-COM     COM1              (Console)

01: MPC8XX-SMC        SMC2

02: MEMORY            CHNL0

------------------------

According to MBX manual, SMC1 is used as console port.

If it's true, COM1 is using SMC1?

So, I thought I must use SMC'1 UART to print out to a console. Is it
correct?

I tested the application using SMC1' s UART

 by applying a SMC's UART application note provided by Motorola's
website(MPC860COD17).

But It doesn't seem to work. I can't see anything from a console after
executing this test application.



Thank you any help.


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