linux-2.4.18 & copy-back cache mode

linux-2.4.18 & copy-back cache mode

[Laurent Pinchart]

Hi everybody

I tried to boot a FADS860T board with the 2.4.18 linux kernel, and
experienced problems with cache set in Copy-Back mode.

The kernel configuration help states that you can say 'Y' to Copy-Back
mode if 'you don't know what that is about', so that's what I did.

I then got a 'kernel access of bad area' just after the 'CPM UART driver
version 0.03' message.

I traced the problem to rs_8xx_init, and found out that a write to .data
was causing the crash.

After some more investigation I found that disabling Copy-Back mode
(thus enabling Write-Through mode) fixed the problem.

The problem seems to have been solved in the linuxppc repository, so the
purpose if this message is not to ask for help but rather to give help
to people who will experience the same problem (no doubt there will be
some, as the Copy-Back mode is advised by the kernel configurator).

Laurent Pinchart

PS: I posted a few patches based on the latest linuxppc tree (to fix
some compilation warnings and a problem with xmon) about one week ago. I
got no feedback. Have they got through to the list ?


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Re: linux-2.4.18 & copy-back cache mode

[Dan Malek]

Laurent Pinchart wrote:


> After some more investigation I found that disabling Copy-Back mode
> (thus enabling Write-Through mode) fixed the problem.

What version of silicon?  Sounds like the "CPU6 errata" that affects
anything less than a Rev. C part.


	-- Dan


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Re: linux-2.4.18 & copy-back cache mode

[Laurent Pinchart]

>
>
>> After some more investigation I found that disabling Copy-Back mode
>> (thus enabling Write-Through mode) fixed the problem.
>
> What version of silicon?  Sounds like the "CPU6 errata" that affects
> anything less than a Rev. C part.

It's a Rev. D.3

Laurent Pinchart


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Re: linux-2.4.18 & copy-back cache mode

[Dan Malek]

Laurent Pinchart wrote:


> It's a Rev. D.3

Hmmmm....I regularly use one of those for testing (maybe it's an 855T),
and it seems OK for me.  The first one I had didn't work well, but
it was tracked down to a UPM/SDRAM timing problem.  People keep talking
about running > 50 MHz bus on these newer parts, is there something
different about the memory controller that allows this and may cause
compatibility problems?  I have (fortunately :-) not looked at this
level of detail in the newer parts.

When you disable copyback you also disable burst mode write from
the CPU core.


	-- Dan


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Re: linux-2.4.18 & copy-back cache mode

[Wolfgang Denk]

In message <3C8643B7.60506@embeddededge.com> you wrote:
>
> it was tracked down to a UPM/SDRAM timing problem.  People keep talking
> about running > 50 MHz bus on these newer parts, is there something
> different about the memory controller that allows this and may cause
> compatibility problems?  I have (fortunately :-) not looked at this
> level of detail in the newer parts.

There are no differences AFAIK. It's just a faster CPU that allows 66
or even 76 MHz with 1:1 CPU/bus clock mode.

We have a MPC823E system here that runs at 66 MHz, and I will have  a
MPC855T  at 66MHz in 18 hours from now. So far I didn't encounter any
problems - of course you have to adjust the UPM tables and what  else
you need to initialize the memory controller.

Wolfgang Denk

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Re: linux-2.4.18 & copy-back cache mode

[Dan Malek]

Wolfgang Denk wrote:

> There are no differences AFAIK. It's just a faster CPU that allows 66
> or even 76 MHz with 1:1 CPU/bus clock mode.

Interesting.  Faster than 50 MHz cores used to require the 2:1 bus
clock division.  I don't remember timing parameters that would
exceed 50 MHz.  Yes, the part will let you do that, but I thought that
was outside of the part specification.  I guess I'll have to take a look.


	-- Dan


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serial console on 405GP

[Kim, Kwansuk]

Dear, everyone!

I'm poring linux-2.4.18-pre7 (from penquinppc.org) on my customized board (with IBM 405GP)

My board has no keyboard, so I'm using serial console on UART0.
I ported ppcboot, and it works well.

When I ported linux on my board, there happened some problem.

After init forks sash (standalone shell as you know),
I can see the prompt of the sash but the character sent wasn't delivered to sash.
So what character I send to the sash. It never respond.

I watch for the serial source (driver/char/serial.c) and enabled DEBUG option and the character sent
was received by kernel.

I don't know why the characters are disappeared.

Anyone know the reason?

Please, help me.

 ==============================================
     Just for fun...
                                                  - Linus Torvalds
 ==============================================
  Kwansuk Kim
  Engineer, NeoWave Inc.
  Tel   +82-31-380-4927    Fax +82-31-380-4747
  E-mail: kskim@neowave.co.kr
==============================================

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Re: serial console on 405GP

[Sangmoon Kim]

Hi, Kim,Kwansuk!

It seams you have the same problem that I had just two weeks ago.
It is likely you have the serial port located below 0xc0000000.
If it is so, I suggest you to move the serial port above 0xc0000000.
If you want to know the reason, just find the mails, in this mailing list, titled "Re: execve system call question"

- Sangmoon Kim -

----- Original Message -----
From: "Kim, Kwansuk" <kskim@neowave.co.kr>
To: <linuxppc-embedded@lists.linuxppc.org>
Sent: Thursday, March 07, 2002 11:42 AM
Subject: serial console on 405GP


>
> Dear, everyone!
>
> I'm poring linux-2.4.18-pre7 (from penquinppc.org) on my customized board (with IBM 405GP)
>
> My board has no keyboard, so I'm using serial console on UART0.
> I ported ppcboot, and it works well.
>
> When I ported linux on my board, there happened some problem.
>
> After init forks sash (standalone shell as you know),
> I can see the prompt of the sash but the character sent wasn't delivered to sash.
> So what character I send to the sash. It never respond.
>
> I watch for the serial source (driver/char/serial.c) and enabled DEBUG option and the character sent
> was received by kernel.
>
> I don't know why the characters are disappeared.
>
> Anyone know the reason?
>
> Please, help me.
>
>  ==============================================
>      Just for fun...
>                                                   - Linus Torvalds
>  ==============================================
>   Kwansuk Kim
>   Engineer, NeoWave Inc.
>   Tel   +82-31-380-4927    Fax +82-31-380-4747
>   E-mail: kskim@neowave.co.kr
> ==============================================
>
>
>

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RE: linux-2.4.18 & copy-back cache mode

[Navin Boppuri]

I am sorry. I meant 64Mhz , not 66Mhz.

Navin.

-----Original Message-----
From: Navin Boppuri
Sent: Thursday, March 07, 2002 2:33 PM
To: linuxppc-embedded@lists.linuxppc.org
Cc: laurent.pinchart@capflow.com
Subject: RE: linux-2.4.18 & copy-back cache mode



I am running my MPC855T at 66Mhz 1:1 CPU/bus clock mode without any problems. I used an app. note from Motorola to do this and according to the app.note, we just need to satisfy some timing constraints on the processor (latency of data reaching the MPC pins from SDRAM). The app. note suggests using specific Micron SDRAM which satisfy all these requirements.

Navin.

-----Original Message-----
From: Dan Malek [mailto:dan@embeddededge.com]
Sent: Wednesday, March 06, 2002 1:50 PM
To: Wolfgang Denk
Cc: laurent.pinchart@capflow.com; linuxppc-embedded@lists.linuxppc.org
Subject: Re: linux-2.4.18 & copy-back cache mode



Wolfgang Denk wrote:

> There are no differences AFAIK. It's just a faster CPU that allows 66
> or even 76 MHz with 1:1 CPU/bus clock mode.

Interesting.  Faster than 50 MHz cores used to require the 2:1 bus
clock division.  I don't remember timing parameters that would
exceed 50 MHz.  Yes, the part will let you do that, but I thought that
was outside of the part specification.  I guess I'll have to take a look.


	-- Dan


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Re: linux-2.4.18 & copy-back cache mode

[Wojciech Kromer]

>
>
>I am sorry. I meant 64Mhz , not 66Mhz.
>
>
>
>
>I am running my MPC855T at 66Mhz 1:1 CPU/bus clock mode without any problems. I used an app. note from Motorola to do this and according to the app.note, we just need to satisfy some timing constraints on the processor (latency of data reaching the MPC pins from SDRAM). The app. note suggests using specific Micron SDRAM which satisfy all these requirements.
>
>Subject: Re: linux-2.4.18 & copy-back cache mode
>
Maybe it's teh same problem.
I have some problems while strong memory usage, for example copying a lot of files.
It stops on bus errors.

Anyone could send me UPM table for CAS_LATENCY==3. I'm not sure if burst is realy needed. Now its disabled, because I do not have correct UPM table for this.


==================================


I have  CPU:   XPC860xxZPnnD4 at 80 MHz: 4 kB I-Cache 4 kB D-Cache FEC present

And SDRAM:

  DIMM size 0x08000000 (128 MB)
  [00] 80  number of bytes written/used
  [01] 08  total number of bytes in serial PD device
  [02] 04  fundamental memory type (SDRAM)
  [03] 0c  number of rows
  [04] 09  number of columns
  [05] 02  number of banks
  [06] 40  data width (lo)
  [07] 00  data width (hi)
  [08] 01  interface levels
  [09] 75  RAS access
  [0A] 54  CAS access
  [0B] 00  configuration type (non-parity/parity/ECC)
  [0C] 80  refresh rate/type
  [0D] 08  primary DRAM organization
  [0E] 00  secondary DRAM organization (parity/ECC-checkbits)
  [0F] 01
  [12] 04  supported CAS latencies: 3
  [1F] 10   bank size (64 MB)
  other:
        0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f
  [1x] 8f 04 04 01 01 00 0e a0 60 00 00 14 0f 14 2c 10
  [2x] 15 08 15 08 00 00 00 00 00 00 00 00 00 00 00 00
  [3x] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 9c
  [4x] 2c ff ff ff ff ff ff ff 01 00 00 00 00 00 00 00
  [5x] 00 00 00 00 00 00 00 00 00 00 00 01 00 ff ff ff
  [6x] ff ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00
  [7x] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 64 fd


setup MEM like this

 UPM 00804000
 MPTPR 00001000
 SDRAM 2 32MB   BR fff00110=0x000000C1 OR fff00114=0xFE000F00
 SDRAM 3 32MB   BR fff00118=0x020000C1 OR fff0011c=0xFE000F00
 SDRAM 5 32MB   BR fff00128=0x040000C1 OR fff0012c=0xFE000F00
 SDRAM 6 32MB   BR fff00130=0x060000C1 OR fff00134=0xFE000F00
 MBMR 4e944112  MAR 000000c8  MCR  80804234 80806234 8080a234 8080c234



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Re: linux-2.4.18 & copy-back cache mode

[Wolfgang Denk]

In message <3C88CDB2.7070905@dgt-lab.com.pl> you wrote:
>
> Anyone could send me UPM table for CAS_LATENCY==3. I'm not sure if burst is realy needed. Now its disabled, because I do not have correct UPM table for this.

Browse the PPCBoot sources;  I  added  a  configuration  for  TQM8xxL
modules   at   66   MHz  (cpu-bus  1:1)  recently;  also,  the  LWMON
configuration runs at 66 MHz 1:1.

Wolfgang Denk

--
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@denx.de
Every time history repeats itself the price goes up.

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Re: linux-2.4.18 & copy-back cache mode

[Wojciech Kromer]

Wolfgang Denk wrote:

>In message <3C88CDB2.7070905@dgt-lab.com.pl> you wrote:
>
>>Anyone could send me UPM table for CAS_LATENCY==3. I'm not sure if burst is realy needed. Now its disabled, because I do not have correct UPM table for this.
>>
>
>Browse the PPCBoot sources;  I  added  a  configuration  for  TQM8xxL
>modules   at   66   MHz  (cpu-bus  1:1)  recently;  also,  the  LWMON
>configuration runs at 66 MHz 1:1.
>
OK, thank You. But this UPM table dosen't seem to work with my DIMM.




>




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Re: linux-2.4.18 & copy-back cache mode

[Wolfgang Denk]

In message <3C8DA95C.7060402@dgt-lab.com.pl> Wojciech Kromer wrote:
>
> >Browse the PPCBoot sources;  I  added  a  configuration  for  TQM8xxL
> >modules   at   66   MHz  (cpu-bus  1:1)  recently;  also,  the  LWMON
> >configuration runs at 66 MHz 1:1.
> >
> OK, thank You. But this UPM table dosen't seem to work with my DIMM.

Probably not. The whole initialization depends  on  the  actual  chip
types; it's Micron SDRAM in our case.

Wolfgang Denk

--
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Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@denx.de
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Re: linux-2.4.18 & copy-back cache mode

[Conn Clark]

Navin Boppuri wrote:
>
> I am sorry. I meant 64Mhz , not 66Mhz.
>
> Navin.
>
> -----Original Message-----
> From: Navin Boppuri
> Sent: Thursday, March 07, 2002 2:33 PM
> To: linuxppc-embedded@lists.linuxppc.org
> Cc: laurent.pinchart@capflow.com
> Subject: RE: linux-2.4.18 & copy-back cache mode
>
> I am running my MPC855T at 66Mhz 1:1 CPU/bus clock mode without any problems. I used an app. note from Motorola to do this and according to the app.note, we just need to satisfy some timing constraints on the processor (latency of data reaching the MPC pins from SDRAM). The app. note suggests using specific Micron SDRAM which satisfy all these requirements.
>
> Navin.

Which app note was this? Does any body know if it will work on an
MPC850?

Thanks,

	Conn
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RE: linux-2.4.18 & copy-back cache mode

[Navin Boppuri]

You will have to whip up a set of UPM words specific for you SDRAM. Wolfgang told me this a million times before I finally got my SDRAM working. Look at your SDRAM datasheet and you should be able to figure out the timing.

Also, there is utility from Motorola `MCUinit 3.1` that has a GUI interface to whip out all the timing for you memory controller. Search for it in google and you should be able to download it.

Navin.


In message <3C8DA95C.7060402@dgt-lab.com.pl> Wojciech Kromer wrote:
>
> >Browse the PPCBoot sources;  I  added  a  configuration  for  TQM8xxL
> >modules   at   66   MHz  (cpu-bus  1:1)  recently;  also,  the  LWMON
> >configuration runs at 66 MHz 1:1.
> >
> OK, thank You. But this UPM table dosen't seem to work with my DIMM.

Probably not. The whole initialization depends  on  the  actual  chip
types; it's Micron SDRAM in our case.

Wolfgang Denk

--
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@denx.de
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