* MPC7455
@ 2002-03-06 7:02 Paul White
2002-03-06 19:46 ` MPC7455 Benjamin Herrenschmidt
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Paul White @ 2002-03-06 7:02 UTC (permalink / raw)
To: linuxppc-dev
Hello!
I've read through the archives of the linuxppc-dev and linuxppc-embedded
mailing lists, and didn't see very much information regarding Linux on
the Motorolai MPC 7455.
I've checked the latest base kernel from kernel.org, 2.4.18, and there
is no 7455 support. I've already done the code to bring Linux up on the
7455, adding it to arch/ppc/kernel/cputable.c, as well as writing a new
setup_cpu_7455, and a new setup_7455_regs function which sets up the
HID0, HID1, and MSSCR0 registers. I am wondering if anyone is interested
in these changes.
In one of the e-mails in the archives, it was suggested to have Linux
configure the 7455 just the same as the 7450, however this will not
work properly. HID0 has changed quite a bit, as well as HID1, thus
requiring a new setup routine. It looks as though the 7451 and 7455
are very similar, and the same init code and restrictions apply, however
between the 7450 and 7451, things have changed quite a bit.
If there is no support out there as of yet, I can create a patch file
and send it off, if anyone is interested.
One thing we ran into regarding the MPC7455, however, is that
it does not guarentee Stores before Loads, meaning if you have
code that has:
Load Instruction
Load Instruction
- This is OK, they will happen in order as long as its Guarded
Store Instruction
Store Instruction
- This is OK, they will happen in order as long as its Guarded
Load Instruction
Store Instruction
- This is OK, they will happen in order as long as its Guarded
Store Instruction
Load Instruction
- This is not guarenteed in order, even if its Guarded
We had to add an eieio to all of our drivers, such as our PCI
driver, which requires a write to one register before reading another.
The eieio must go between the store and the load.
Just a heads up, if no one has tried the 7455 yet! Let me know
if anyone is interested in the 7455 changes I've done.
Paul White
Senior Engineer, Software
Bivio Networks, Inc.
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: MPC7455
2002-03-06 7:02 MPC7455 Paul White
@ 2002-03-06 19:46 ` Benjamin Herrenschmidt
2002-03-07 5:59 ` MPC7455 Paul White
2002-03-07 9:24 ` MPC7455 Gabriel Paubert
2002-03-06 22:18 ` MPC7455 Kevin B. Hendricks
2002-03-07 8:41 ` MPC7455 Giuliano Pochini
2 siblings, 2 replies; 10+ messages in thread
From: Benjamin Herrenschmidt @ 2002-03-06 19:46 UTC (permalink / raw)
To: Paul White, linuxppc-dev
>
>Hello!
>
>I've read through the archives of the linuxppc-dev and linuxppc-embedded
>mailing lists, and didn't see very much information regarding Linux on
>the Motorolai MPC 7455.
>
>I've checked the latest base kernel from kernel.org, 2.4.18, and there
>is no 7455 support. I've already done the code to bring Linux up on the
>7455, adding it to arch/ppc/kernel/cputable.c, as well as writing a new
>setup_cpu_7455, and a new setup_7455_regs function which sets up the
>HID0, HID1, and MSSCR0 registers. I am wondering if anyone is interested
>in these changes.
Please, send them to me. I have some 7455 support in my rsync tree
that I am about to push to bk. However, some of the registers, like
HID1 or MSSCR0, I consider have to be setup by the firmware or by
machine specific code.
>In one of the e-mails in the archives, it was suggested to have Linux
>configure the 7455 just the same as the 7450, however this will not
>work properly. HID0 has changed quite a bit, as well as HID1, thus
>requiring a new setup routine. It looks as though the 7451 and 7455
>are very similar, and the same init code and restrictions apply, however
>between the 7450 and 7451, things have changed quite a bit.
>
>If there is no support out there as of yet, I can create a patch file
>and send it off, if anyone is interested.
>
>One thing we ran into regarding the MPC7455, however, is that
>it does not guarentee Stores before Loads, meaning if you have
>code that has:
>
>Load Instruction
>Load Instruction
> - This is OK, they will happen in order as long as its Guarded
>
>Store Instruction
>Store Instruction
> - This is OK, they will happen in order as long as its Guarded
>
>Load Instruction
>Store Instruction
> - This is OK, they will happen in order as long as its Guarded
>
>Store Instruction
>Load Instruction
> - This is not guarenteed in order, even if its Guarded
Ah ? I missed that in the doc. It's pretty bad though so far, all
drivers are supposed to eieio on any IO access anyway.
>We had to add an eieio to all of our drivers, such as our PCI
>driver, which requires a write to one register before reading another.
>The eieio must go between the store and the load.
eieio is done within common IO macros like readl/writel, in/out_le/beXX
etc...
>Just a heads up, if no one has tried the 7455 yet! Let me know
>if anyone is interested in the 7455 changes I've done.
My current tree boots and appear to work on Apple dual G4 1Ghz which is
7455 based.
I'm still interested in your patches as I may have missed something.
Regards,
Ben.
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: MPC7455
2002-03-06 19:46 ` MPC7455 Benjamin Herrenschmidt
@ 2002-03-07 5:59 ` Paul White
2002-03-06 21:48 ` MPC7455 benh
2002-03-07 9:24 ` MPC7455 Gabriel Paubert
1 sibling, 1 reply; 10+ messages in thread
From: Paul White @ 2002-03-07 5:59 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
On Wed, 6 Mar 2002, Benjamin Herrenschmidt wrote:
> Please, send them to me. I have some 7455 support in my rsync tree
> that I am about to push to bk. However, some of the registers, like
> HID1 or MSSCR0, I consider have to be setup by the firmware or by
> machine specific code.
Yes - It seems this is what Linux expects for the 7450 as well,
as it requests the firmware setup the CPU.
In my 7455 setup, I setup the CPU in linux, assuming the firmware
hasn't done anything yet. Things such as Address Broadcast Enable
bits are now in HID1 instead of HID0 as on other processors. As
for cache snooping, the 7455 defaults to a different method of
External Data Intervention. Maybe this is something firmware
usually sets up? Using the Galileo system controller, we had to
disable this mode to make it compatable to the MPC7410.
> >Store Instruction
> >Load Instruction
> > - This is not guarenteed in order, even if its Guarded
>
> Ah ? I missed that in the doc. It's pretty bad though so far, all
> drivers are supposed to eieio on any IO access anyway.
See section 3.3.3.5, page 3-29 of the 7450/7455 Users manual.. Its
good that everything already does eieio's between IO accesses. We
(being our driver engineers here) are kicking ourselves for not
adding these into our custom drivers. We've added them now, and
things seem to work great!
> My current tree boots and appear to work on Apple dual G4 1Ghz which is
> 7455 based.
>
> I'm still interested in your patches as I may have missed something.
Great! It sounds like the firmware is doing everyhting. It might be
nice to add an option to have linux configure the CPU registers or not,
as for us embedded guys thats easier than implimenting it all in the
firmware. We can do it either way now that we know what the registers
should be, though.
I'll have a cleaned up patch file by tomorrow evening. What tree
would you prefer the patch be against?
Paul W.
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: MPC7455
2002-03-07 5:59 ` MPC7455 Paul White
@ 2002-03-06 21:48 ` benh
2002-03-07 15:30 ` MPC7455 Tom Rini
0 siblings, 1 reply; 10+ messages in thread
From: benh @ 2002-03-06 21:48 UTC (permalink / raw)
To: Paul White; +Cc: linuxppc-dev
>Great! It sounds like the firmware is doing everyhting. It might be
>nice to add an option to have linux configure the CPU registers or not,
>as for us embedded guys thats easier than implimenting it all in the
>firmware. We can do it either way now that we know what the registers
>should be, though.
Well, then the correct place for the patch is probably in the wrapper
or in a CONFIG_xxx option for your embedded box. At least for PReP/CHRP/Pmac,
I want to rely on the firmware for various reasons (one beeing that Apple's
firmware sets some bits in specific ways to avoid/workaround chip errata).
>I'll have a cleaned up patch file by tomorrow evening. What tree
>would you prefer the patch be against?
Whatever, I'll probably edit it anyway.
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: MPC7455
2002-03-06 21:48 ` MPC7455 benh
@ 2002-03-07 15:30 ` Tom Rini
2002-03-07 16:45 ` MPC7455 Dan Malek
0 siblings, 1 reply; 10+ messages in thread
From: Tom Rini @ 2002-03-07 15:30 UTC (permalink / raw)
To: benh; +Cc: Paul White, linuxppc-dev
On Wed, Mar 06, 2002 at 10:48:49PM +0100, benh@kernel.crashing.org wrote:
>
> >Great! It sounds like the firmware is doing everyhting. It might be
> >nice to add an option to have linux configure the CPU registers or not,
> >as for us embedded guys thats easier than implimenting it all in the
> >firmware. We can do it either way now that we know what the registers
> >should be, though.
>
> Well, then the correct place for the patch is probably in the wrapper
> or in a CONFIG_xxx option for your embedded box. At least for PReP/CHRP/Pmac,
> I want to rely on the firmware for various reasons (one beeing that Apple's
> firmware sets some bits in specific ways to avoid/workaround chip errata).
I'd think that outside of CONFIG_ALL_PPC (or wherever CHRP/Pmac end up
in 2.5.x) we don't care what the firmware did.
Unless of course we move all of the CPU-mucking into arch/ppc/boot, and
just pass along a CPU bi rec (or do what we do now, either way...)
--
Tom Rini (TR1265)
http://gate.crashing.org/~trini/
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: MPC7455
2002-03-07 15:30 ` MPC7455 Tom Rini
@ 2002-03-07 16:45 ` Dan Malek
0 siblings, 0 replies; 10+ messages in thread
From: Dan Malek @ 2002-03-07 16:45 UTC (permalink / raw)
To: Tom Rini; +Cc: benh, Paul White, linuxppc-dev
Tom Rini wrote:
> I'd think that outside of CONFIG_ALL_PPC (or wherever CHRP/Pmac end up
> in 2.5.x) we don't care what the firmware did.
That's a very good point. Anything we do inside of the kernel with
cputable/features must be generic to all of the boards we support. If
there is something unique (which is always the case of embedded boards :-),
that needs to be done in the bootloader before we get to the kernel or
in the board specific setup files for the platform.
-- Dan
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: MPC7455
2002-03-06 19:46 ` MPC7455 Benjamin Herrenschmidt
2002-03-07 5:59 ` MPC7455 Paul White
@ 2002-03-07 9:24 ` Gabriel Paubert
1 sibling, 0 replies; 10+ messages in thread
From: Gabriel Paubert @ 2002-03-07 9:24 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Paul White, linuxppc-dev
On Wed, 6 Mar 2002, Benjamin Herrenschmidt wrote:
>
> >
> >Hello!
> >
> >I've read through the archives of the linuxppc-dev and linuxppc-embedded
> >mailing lists, and didn't see very much information regarding Linux on
> >the Motorolai MPC 7455.
> >
> >I've checked the latest base kernel from kernel.org, 2.4.18, and there
> >is no 7455 support. I've already done the code to bring Linux up on the
> >7455, adding it to arch/ppc/kernel/cputable.c, as well as writing a new
> >setup_cpu_7455, and a new setup_7455_regs function which sets up the
> >HID0, HID1, and MSSCR0 registers. I am wondering if anyone is interested
> >in these changes.
>
> Please, send them to me. I have some 7455 support in my rsync tree
> that I am about to push to bk. However, some of the registers, like
> HID1 or MSSCR0, I consider have to be setup by the firmware or by
> machine specific code.
>
> >In one of the e-mails in the archives, it was suggested to have Linux
> >configure the 7455 just the same as the 7450, however this will not
> >work properly. HID0 has changed quite a bit, as well as HID1, thus
> >requiring a new setup routine. It looks as though the 7451 and 7455
> >are very similar, and the same init code and restrictions apply, however
> >between the 7450 and 7451, things have changed quite a bit.
> >
> >If there is no support out there as of yet, I can create a patch file
> >and send it off, if anyone is interested.
> >
> >One thing we ran into regarding the MPC7455, however, is that
> >it does not guarentee Stores before Loads, meaning if you have
> >code that has:
> >
> >Load Instruction
> >Load Instruction
> > - This is OK, they will happen in order as long as its Guarded
> >
> >Store Instruction
> >Store Instruction
> > - This is OK, they will happen in order as long as its Guarded
> >
> >Load Instruction
> >Store Instruction
> > - This is OK, they will happen in order as long as its Guarded
I have never seen any processor making a store bypass a load. thta's
obvious for performance reasons.
> >
> >Store Instruction
> >Load Instruction
> > - This is not guarenteed in order, even if its Guarded
>
> Ah ? I missed that in the doc. It's pretty bad though so far, all
> drivers are supposed to eieio on any IO access anyway.
It was always the case, starting with 603 at least. In this case it is
only guaranteed to be in order if the store and load addresses are the
same. The 601 did not have the guarded bit so it's different...
Guarded means only that it won't reordered to a point where the access
becomes speculative, i.e., an intruction before that access could
generate an internal exception (machine checks are another story).
I saw this kind of behaviour in a VME driver on a 603e. That's because I
defined the vme_{read,write}{8,16,32} not to do an eieio and defined
explicit ordering barriers: read after write is vme_raw_barrier, but there
is no need for vme_war_barrier (world peace is on its way :-)).
Regards,
Gabriel
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: MPC7455
2002-03-06 7:02 MPC7455 Paul White
2002-03-06 19:46 ` MPC7455 Benjamin Herrenschmidt
@ 2002-03-06 22:18 ` Kevin B. Hendricks
2002-03-07 6:01 ` MPC7455 Paul White
2002-03-07 8:41 ` MPC7455 Giuliano Pochini
2 siblings, 1 reply; 10+ messages in thread
From: Kevin B. Hendricks @ 2002-03-06 22:18 UTC (permalink / raw)
To: Paul White, linuxppc-dev
Hi,
> I've checked the latest base kernel from kernel.org, 2.4.18, and there
> is no 7455 support. I've already done the code to bring Linux up on the
> 7455, adding it to arch/ppc/kernel/cputable.c, as well as writing a new
> setup_cpu_7455, and a new setup_7455_regs function which sets up the
> HID0, HID1, and MSSCR0 registers. I am wondering if anyone is interested
> in these changes.
Yes, I am.
> In one of the e-mails in the archives, it was suggested to have Linux
> configure the 7455 just the same as the 7450, however this will not
> work properly. HID0 has changed quite a bit, as well as HID1, thus
> requiring a new setup routine. It looks as though the 7451 and 7455
> are very similar, and the same init code and restrictions apply, however
> between the 7450 and 7451, things have changed quite a bit.
Hmm, that's funny. My Dual 1 Gig G4 machine (7455) runs quite well (so
far) with using the 7450 setup for the HID registers after adding the
entries for detecting the 7455. The bits that changed in HID0 are not
played with in the 7450 setup so it should be okay (it seems to be
working) shouldn't it?
> If there is no support out there as of yet, I can create a patch file
> and send it off, if anyone is interested.
Yes I would very much like to see it.
> One thing we ran into regarding the MPC7455, however, is that
> it does not guarentee Stores before Loads, meaning if you have
> code that has:
>
> Load Instruction
> Load Instruction
> - This is OK, they will happen in order as long as its Guarded
>
> Store Instruction
> Store Instruction
> - This is OK, they will happen in order as long as its Guarded
>
> Load Instruction
> Store Instruction
> - This is OK, they will happen in order as long as its Guarded
>
> Store Instruction
> Load Instruction
> - This is not guarenteed in order, even if its Guarded
>
> We had to add an eieio to all of our drivers, such as our PCI
> driver, which requires a write to one register before reading another.
> The eieio must go between the store and the load.
>
> Just a heads up, if no one has tried the 7455 yet! Let me know
> if anyone is interested in the 7455 changes I've done.
Thanks,
Kevin
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: MPC7455
2002-03-06 22:18 ` MPC7455 Kevin B. Hendricks
@ 2002-03-07 6:01 ` Paul White
0 siblings, 0 replies; 10+ messages in thread
From: Paul White @ 2002-03-07 6:01 UTC (permalink / raw)
To: Kevin B. Hendricks; +Cc: linuxppc-dev
On Wed, 6 Mar 2002, Kevin B. Hendricks wrote:
> Hmm, that's funny. My Dual 1 Gig G4 machine (7455) runs quite well (so
> far) with using the 7450 setup for the HID registers after adding the
> entries for detecting the 7455. The bits that changed in HID0 are not
> played with in the 7450 setup so it should be okay (it seems to be
> working) shouldn't it?
Well it seems as though the G4 machines are setting up the CPU registers
in firmware, thus linux doesn't have to do anything. On our board, our
firmware doesn't do this so we wanted to set the registers up in Linux.
> Yes I would very much like to see it.
Sure...I'll have a cleaned up patch file ready tomorrow evening, I
can e-mail it to the group here.
Paul W.
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: MPC7455
2002-03-06 7:02 MPC7455 Paul White
2002-03-06 19:46 ` MPC7455 Benjamin Herrenschmidt
2002-03-06 22:18 ` MPC7455 Kevin B. Hendricks
@ 2002-03-07 8:41 ` Giuliano Pochini
2 siblings, 0 replies; 10+ messages in thread
From: Giuliano Pochini @ 2002-03-07 8:41 UTC (permalink / raw)
To: Paul White; +Cc: linuxppc-dev
> One thing we ran into regarding the MPC7455, however, is that
> it does not guarentee Stores before Loads, meaning if you have
> code that has:
Argh! This one affects user level drivers too. X developers should be warned.
Bye.
** Sent via the linuxppc-dev mail list. See http://lists.linuxppc.org/
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2002-03-07 16:45 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
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2002-03-06 7:02 MPC7455 Paul White
2002-03-06 19:46 ` MPC7455 Benjamin Herrenschmidt
2002-03-07 5:59 ` MPC7455 Paul White
2002-03-06 21:48 ` MPC7455 benh
2002-03-07 15:30 ` MPC7455 Tom Rini
2002-03-07 16:45 ` MPC7455 Dan Malek
2002-03-07 9:24 ` MPC7455 Gabriel Paubert
2002-03-06 22:18 ` MPC7455 Kevin B. Hendricks
2002-03-07 6:01 ` MPC7455 Paul White
2002-03-07 8:41 ` MPC7455 Giuliano Pochini
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