enet rx doesn't work

enet rx doesn't work

[Walser, Martin]

Hi,

I've tried to use the enet over the LXT905. Tx seems to work, but I'm not able
to receive data from it.
I've measured the rxd, rclk and rena pins (the RENA signal is aktive high), but
they seems to be ok too.

But I get no rx interrupt, the scc_enet_interrupt is never called when receiving
data.

I'm using kernel 2.4.4 from denx.

Any ideas?

Martin


** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

Re: enet rx doesn't work

[Wolfgang Denk]

In message <8D4C69676E66D511A1CB00508BBBB1921BCF0C@ranmx1.ran.harris.com> you wrote:
>
> I've tried to use the enet over the LXT905. Tx seems to work, but I'm not able
> to receive data from it.
> I've measured the rxd, rclk and rena pins (the RENA signal is aktive high), but
> they seems to be ok too.
>
> But I get no rx interrupt, the scc_enet_interrupt is never called when receiving
> data.

Checked the pin configuration and the clock routing?

Wolfgang Denk

--
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@denx.de
There's another way to survive.  Mutual trust -- and help.
	-- Kirk, "Day of the Dove", stardate unknown

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/

enet rx doesn't work

[Walser, Martin]

Hi,

I've tested the rx clock routing, this is ok.
All other signals seem to be ok (COL is low, CD is high when receiving a frame).

So I don't know what should be wrong.

That's the configuration of my board.

/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC2 use.
 */
#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
#define PA_ENET_RCLK	((ushort)0x0400)	/* PA  5 */
#define PA_ENET_TCLK	((ushort)0x0800)	/* PA  4 */

#define PC_ENET_TENA	((ushort)0x0002)	/* PC 14 */
#define PC_ENET_CLSN	((ushort)0x0040)	/* PC 9 */
#define PC_ENET_RENA	((ushort)0x0080)	/* PC 8 */

/* Control bits in the SICR to route TCLK (CLK4) and RCLK (CLK3) to
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 */
#define SICR_ENET_MASK	((uint)0x0000ff00)
#define SICR_ENET_CLKRT	((uint)0x00003700)


Best regards
Martin

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/